Multithreaded kernel for graphics processing unit

• US 7,673,304 B2
• Filed: 01/22/2004
• Issued: 03/02/2010
• Est. Priority Date: 02/18/2003
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Gosalia, Anuj B., Pronovost, Steve
• Primary Examiner(s): An; Meng-Ai
• Assistant Examiner(s): To; Jennifer N
• Application Number:
  US10/763,777
• Publication Number:
  US 20040160446A1
• Time in Patent Office: 2,231 Days
• Field of Search: 718102-108, 719/328, 345/418, 345/542
• US Class Current: 718/102
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/461 Saving or restoring of program or task context
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system
• CPC Class Codes: G06F 9/5016 the resource being the memory
• CPC Class Codes: G06F 9/5038 considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration scheduling strategies G06F9/4881 and subgroups
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes
• CPC Class Codes: G06F 9/546 Message passing systems or structures, e.g. queues
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems and methods are provided for scheduling the processing of a coprocessor whereby applications can submit tasks to a scheduler, and the scheduler can determine how much processing each application is entitled to as well as an order for processing. In connection with this process, tasks that require processing can be stored in physical memory or in virtual memory that is managed by a memory manager. The invention also provides various techniques of determining whether a particular task is ready for processing. A “run list” may be employed to ensure that the coprocessor does not waste time between tasks or after an interruption. The invention also provides techniques for ensuring the security of a computer system, by not allowing applications to modify portions of memory that are integral to maintaining the proper functioning of system operations.

Claims

1. A method for scheduling tasks for processing by a coprocessor, comprising:

gathering tasks for processing by a coprocessor into a user mode command buffer memory group, said tasks relating to a first application, wherein at least a portion of the user mode command buffer is allocated in a context of said first application;

delivering the tasks to a scheduler wherein scheduler functions include determining an order for processing the tasks wherein the order may include tasks that relate to one or more other applications;

determining an order for processing the tasks wherein the order accounts for any relative priority among the first application relating to said tasks and one or more other applications relating to additional tasks, and a corresponding amount of processing time that the first application and one or more other applications are entitled to;

preparing tasks for processing by ensuring that any needed memory resources are available in a coprocessor-accessible memory location wherein the preparing tasks occurs in the order determined by the scheduler; and

submitting tasks prepared according to the preparing to the coprocessor for processing.

2. A method according to claim 1 wherein the coprocessor includes a graphics processing unit (GPU).

3. A method according to claim 1, further comprising calling an Application Program Interface (API) when the first application has one or more tasks that require processing by the coprocessor.

4. A method according to claim 3, further comprising calling a user mode driver wherein the functions of the user mode driver include placing rendering commands associated with the one or more tasks in the user mode command buffer memory group.

5. A method according to claim 4, further comprising returning the rendering commands to the API, and submitting them to a coprocessor kernel.

6. A method according to claim 1, further comprising generating a Direct Memory Access (DMA) buffer by a kernel mode driver wherein one or more tasks that require processing by the coprocessor are used to generate the DMA buffer, and the DMA buffer represents the one or more tasks used to generate the DMA buffer.

7. A method according to claim 6, further comprising generating a list of memory resources by the kernel mode driver wherein the memory resources represented by the list are needed by the coprocessor to process one or more tasks represented by the DMA buffer.

8. A method according to claim 7, further comprising building a paging buffer for bringing the memory resources on the list of memory resources to correct memory addresses within the coprocessor-accessible memory location.

9. A method according to claim 1 wherein said preparing is accomplished by a preparation thread which calls a memory manager process capable of determining a location in the coprocessor-accessible memory location to page any needed memory resources.

10. A method according to claim 9, further comprising splitting a DMA buffer when the memory manager process determines that there is not enough room in the coprocessor-accessible memory location to page all needed memory resources.

11. The method of claim 1, wherein computer executable instructions for performing said method are stored on a computer readable medium.

12. The method of claim 1, wherein computer executable instructions for performing at least a portion of said method are received via a modulated data signal.

13. The method of claim 1, wherein said method is carried out on a computing device.

14. A method for scheduling tasks for processing by a coprocessor, comprising:

gathering tasks for processing by a coprocessor into a user mode command buffer memory group, said tasks relating to a first application, wherein at least a portion of the user mode command buffer is allocated in a context of said first application;

delivering the tasks to a scheduler wherein the functions of the scheduler include determining an order for processing the tasks wherein the order may include tasks that relate to one or more other applications;

determining an order for processing the tasks wherein the order accounts for any relative priority among the first application relating to said tasks and one or more other applications relating to additional tasks, and a corresponding amount of processing time that the first application and one or more other applications are entitled to;

preparing tasks for processing by ensuring that any needed memory resources are available in a coprocessor-accessible memory location wherein the preparing tasks occurs in the order determined by the scheduler; and

submitting tasks to the coprocessor for processing;

managing the coprocessor accessible memory to apportion the coprocessor accessible memory among the various tasks; and

providing a per-context virtual address space for the tasks.

15. A method according to claim 14 wherein the coprocessor is a graphics processing unit (GPU).

16. A method according to claim 14, further comprising storing a task in a DMA buffer wherein the storing is accomplished by a user mode driver.

17. A method according to claim 16, further comprising validating a memory resource referenced in a resource list that is associated with the DMA buffer wherein validating entails finding a range of coprocessor-readable memory that is free and asking the kernel mode driver to map a page table or a memory resource handle to that range.

18. A method according to claim 14 wherein the virtual address space is virtualized through the use of a flat page table that divides coprocessor-readable memory into pages of a predefined memory amount wherein further a page table is provided in the virtual address space that contains identifiers for specifying coprocessor-readable memory addresses.

19. A method according to claim 14 wherein the virtual address space is virtualized through the use of a multi-level page table that divides coprocessor-readable memory into pages of a predefined memory amount wherein further a multiple page tables are provided in the virtual address space that contain identifiers for specifying coprocessor-readable memory addresses.

20. A method according to claim 14 wherein a portion of coprocessor readable memory is used to indicate whether all required memory resources associated with a task that requires processing are available in coprocessor-readable memory.

21. The method of claim 14, wherein computer executable instructions for performing said method are stored on a computer readable medium.

22. The method of claim 14, wherein computer executable instructions for performing at least a portion of said method are received via a modulated data signal.

23. The method of claim 14, wherein said method is carried out on a computing device.

24. A method according to claim 14, further comprising:

assigning a base address for a display surface wherein the display surface is allocated contiguously in coprocessor-readable memory; and

delivering a task to the scheduler wherein processing the task will reassign the base address for a display surface.

25. A method according to claim 24 wherein processing the task will reassign the base address for a display surface immediately.

26. A method according to claim 24 wherein processing the task will reassign the base address for a display surface upon the occurrence of a subsequent display synchronization period.

27. A method for scheduling tasks for processing by a coprocessor, comprising:

receiving at an Application Programming Interface (API) calls from a first application, said calls requesting tasks requiring processing by a coprocessor;

sending by said API said tasks to a user mode driver for storage in a command buffer memory group, wherein at least a portion of the command buffer is allocated in a context of said first application;

receiving by said API said tasks from said command buffer pursuant to a flush of said command buffer;

sending by said API said tasks to a coprocessor kernel for processing;

delivering the tasks, by the coprocessor kernel, to a coprocessor scheduler wherein coprocessor scheduler functions include determining an order for processing the tasks, wherein the order may include tasks that relate to one or more other applications, wherein the order accounts for any relative priority among the first application relating to said tasks and the one or more other applications relating to additional tasks and a corresponding amount of processing time that the first application and the one or more other applications are entitled to;

preparing tasks for processing by ensuring that any needed memory resources are available in a coprocessor-accessible memory location wherein the preparing tasks occurs in the order determined by the coprocessor scheduler; and

submitting the prepared tasks to the coprocessor for processing.

28. The method of claim 27 wherein the API operates in conformity with a Direct3D Runtime API.

29. The method of claim 27 wherein the coprocessor kernel operates in conformity with a DirectX Kernel.

30. The method of claim 27, further comprising generating a Direct Memory Access (DMA) buffer by a kernel mode driver wherein one or more tasks that require processing by the coprocessor are used to generate the DMA buffer, and the DMA buffer represents the one or more tasks used to generate the DMA buffer.

31. The method of claim 30, further comprising generating a list of memory resources by the kernel mode driver wherein the memory resources represented by the list are needed by the coprocessor to process one or more tasks represented by the DMA buffer.

32. The method of claim 31, further comprising building a paging buffer for bringing the memory resources on the list of memory resources to correct memory addresses within the coprocessor-accessible memory location.

33. A computer readable storage medium comprising computer executable instructions for scheduling tasks for processing by a coprocessor, comprising:

instructions for receiving at an Application Programming Interface (API) calls from a first application, said calls requesting tasks requiring processing by a coprocessor;

instructions for sending by said API said tasks to a user mode driver for storage in a command buffer memory group, wherein at least a portion of the command buffer is allocated in a context of said first application;

instructions for receiving by said API said tasks from said command buffer pursuant to a flush of said command buffer;

instructions for sending by said API said tasks to a coprocessor kernel for processing;

instructions for delivering the tasks, by the coprocessor kernel, to a coprocessor scheduler wherein coprocessor scheduler functions include determining an order for processing the tasks, wherein the order may include tasks that relate to one or more other applications, wherein the order accounts for any relative priority among the first application relating to said tasks and the one or more other applications relating to additional tasks and a corresponding amount of processing time that the first application and the one or more other applications are entitled to;

instructions for preparing tasks for processing by ensuring that any needed memory resources are available in a coprocessor-accessible memory location wherein the preparing tasks occurs in the order determined by the coprocessor scheduler; and

instructions for submitting the prepared tasks to the coprocessor for processing.

34. The computer readable storage medium of claim 33 wherein the API operates in conformity with a Direct3D Runtime API.

35. The computer readable storage medium of claim 33 wherein the coprocessor kernel operates in conformity with a DirectX Kernel.

36. The computer readable storage medium of claim 33, further comprising instructions for generating a Direct Memory Access (DMA) buffer by a kernel mode driver wherein one or more tasks that require processing by the coprocessor are used to generate the DMA buffer, and the DMA buffer represents the one or more tasks used to generate the DMA buffer.

37. The computer readable storage medium of claim 36, further comprising instructions for generating a list of memory resources by the kernel mode driver wherein the memory resources represented by the list are needed by the coprocessor to process one or more tasks represented by the DMA buffer.

38. The computer readable storage medium of claim 37, further comprising instructions for building a paging buffer for bringing the memory resources on the list of memory resources to correct memory addresses within the coprocessor-accessible memory location.