Feature dimension control in a manufacturing process

• US 7,674,350 B2
• Filed: 01/22/2007
• Issued: 03/09/2010
• Est. Priority Date: 01/22/2007
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Lian, Jingyu, Sarma, Chandrasekhar, Lipinski, Matthias, Zhuang, Haoren, Gutmann, Alois
• Primary Examiner(s): Pert; Evan
• Application Number:
  US11/625,575
• Publication Number:
  US 20080176344A1
• Time in Patent Office: 1,142 Days
• Field of Search: 438/8, 438/9, 156/345.22, 156/345, 156/24, 156/345.31
• US Class Current: 156/345.22
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14

Abstract

A method for manufacturing a semiconductor device is disclosed including determining a dimension or other physical characteristic of a pattern in a layer of material that is disposed on a workpiece, and etching the layer of material using information that is related to the dimension. A system is also disclosed for manufacturing a semiconductor device including a first etch system configured to etch a layer to define a pattern in the layer, and a second etch system configured to measure a physical characteristic of the pattern, determine an etch control parameter based on the physical characteristic, and etch the layer in accordance with the etch control parameter.

Claims

1. A system for manufacturing a semiconductor device, comprising:

a first etch system configured to etch a layer to define a pattern in the layer; and

a second etch system configured to measure a physical characteristic of the pattern, determine an etch control parameter based on the physical characteristic, and etch the layer in accordance with the etch control parameter.

2. The system of claim 1, wherein the first etch system comprises a reactive ion etcher.

3. The system of claim 1, wherein the second etch system is configured to perform a chemical downstream etch process to etch the layer.

4. The system of claim 1, wherein the second etch system comprises a scatterometer configured to detect the physical characteristic.

6. The system of claim 1, wherein the first etch system is configured to perform anisotropic etching of the layer, and the second etch system is configured to perform isotropic etching of the layer in accordance with the etch control parameter.

7. The system of claim 1, wherein the first etch system is configured to perform reactive ion etching of the layer, and the second etch system is configured to perform chemical downstream etching of the layer in accordance with the etch control parameter.

8. The system of claim 1, wherein the first etch system is configured to perform a first type of etching, and the second etch system is configured to perform a second type of etching, different from the first type of etching, in accordance with the etch control parameter.

9. The system of claim 1, wherein the second etch system is a different physical etch system than the first etch system.

10. The system of claim 1, wherein the second etch system is configured to measure the physical characteristic of the pattern after the first etch system has stopped etching the layer.

11. The system of claim 1, wherein the physical characteristic comprises a width of a feature formed in the pattern of the layer.

5. A system for manufacturing a semiconductor wafer, comprising:

means for etching a layer to define a pattern in the layer; and

means for measuring a physical characteristic of the pattern;

means for determining an etch control parameter based on the physical characteristic; and

means for etching the layer in accordance with the etch control parameter.

12. The system of claim 5, wherein the means for etching the layer to define the pattern in the layer is for performing anisotropic etching of the layer, and the means for etching the layer in accordance with the etch control parameter is for performing isotropic etching of the layer in accordance with the etch control parameter.

13. The system of claim 5, wherein the means for etching the layer to define the pattern in the layer is for performing reactive ion etching of the layer, and the means for etching the layer in accordance with the etch control parameter is for performing chemical downstream etching of the layer in accordance with the etch control parameter.

14. The system of claim 5, wherein the means for etching the layer to define the pattern in the layer is for performing a first type of etching, and the means for etching the layer in accordance with the etch control parameter is for performing a second type of etching, different from the first type of etching, in accordance with the etch control parameter.

15. The system of claim 5, wherein the means for etching the layer in accordance with the etch control parameter is a different physical etch system than the means for etching the layer to define the pattern in the layer.

16. The system of claim 5, wherein the means for determining is for determining the etch control parameter after the means for etching the layer to define the pattern in the layer has stopped etching the layer.

17. The system of claim 5, wherein the physical characteristic comprises a width of a feature formed in the pattern of the layer.

18. A system for manufacturing a semiconductor device, comprising:

a first etch system configured to etch a layer disposed on a substrate to define a pattern in the layer; and

a second etch system configured to physically receive the etched substrate after etching is completed by the first etch system, to measure a feature width of the pattern in the layer on the received substrate, and to etch the layer in a manner based on the measured feature width.