Strained complementary metal oxide semiconductor (CMOS) on rotated wafers and methods thereof

• US 7,675,055 B2
• Filed: 10/26/2007
• Issued: 03/09/2010
• Est. Priority Date: 04/22/2005
• Status: Expired due to Fees

• Current Assignee: Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: International Business Machines Corporation
• Inventors: Ouyang, Qiging C., Rim, Kern, Ieong, Meikei
• Primary Examiner(s): Tran; Long K
• Application Number:
  US11/925,088
• Publication Number:
  US 20080042215A1
• Time in Patent Office: 865 Days
• Field of Search: 257/19, 257/55, 257/368, 257/371, 257/372, 257/616, 257/628, 257/E27.062, 257/E27.063, 257/E27.066, 257/E29.139
• US Class Current: 257/19
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

The present invention provides CMOS structures including at least one strained pFET that is located on a rotated semiconductor substrate to improve the device performance. Specifically, the present invention utilizes a Si-containing semiconductor substrate having a (100) crystal orientation in which the substrate is rotated by about 45° such that the CMOS device channels are located along the <100> direction. Strain can be induced upon the CMOS structure including at least a pFET and optionally an nFET, particularly the channels, by forming a stressed liner about the FET, by forming embedded stressed wells in the substrate, or by utilizing a combination of embedded stressed wells and a stressed liner. The present invention also provides methods for fabricating the aforesaid semiconductor structures.

Claims

1. A complementary metal oxide semiconductor (CMOS) structure comprising:

a rotated Si-containing semiconductor substrate having a (100) crystal orientation and a wafer notch along the <

100>

direction;

at least one pFET located on a first region of said rotated Si-containing semiconductor substrate, said at least one pFET having a channel that is along said <

100>

direction;

at least one first stressed well located within the first region of said rotated Si-containing semiconductor substrate that induces a stress on said channel of each pFET, wherein said at least one first stressed well includes a compressively strained material of Si or Si containing at least one of C and Ge;

at least one nFET located on a second region of said rotated Si-containing semiconductor substrate, said at least one nFET having a channel that is along said <

100>

direction;

at least one second stressed well located within the second region of said rotated Si-containing semiconductor substrate that induces a stress on said channel of each nFET, wherein said at least one second stressed well includes a tensile strained material of Si or SiC; and

a tensile strain inducing liner present in the first region over the at least one nFET and in the second region over the at least one pFET, wherein the tensile strain inducing liner has a substantially equal strain in both the first region and the second region.

2. The CMOS structure of claim 1 wherein said rotated Si-containing semiconductor substrate comprises a Si-containing semiconductor material selected from the group consisting of Si, SiGe, SiC, SiGeC, silicon-on-insulators, silicon germanium-on insulators and combinations thereof.

3. The CMOS structure of claim 1 wherein said rotated Si-containing semiconductor substrate is strained, unstrained or a combination of strained and unstrained layers.

4. The CMOS structure of claim 1 further comprising at least one isolation region located within said rotated Si-containing semiconductor substrate.

5. The CMOS structure of claim 1 wherein said at least one pFET comprises a gate dielectric, a gate conductor, at least one sidewall spacer, source/drain extensions and source/drain regions.

6. The CMOS structure of claim 1 wherein said embedded stressed well comprises SiGe.

7. The CMOS structure of claim 1 wherein said stressed well includes source and drain diffusion regions and source and drain extension regions.