Multi-phase delay locked loop with equally-spaced phases over a wide frequency range and method thereof

• US 7,675,333 B2
• Filed: 06/10/2007
• Issued: 03/09/2010
• Est. Priority Date: 06/09/2006
• Status: Expired due to Fees

• Current Assignee: Cosmic Circuits Pvt., Ltd. (Cadence Group)
• Original Assignee: Cosmic Circuits Pvt., Ltd. (Cadence Group)
• Inventors: Ganesan, Sriram, Bhowmik, Prasenjit, Krishnan, Sundararajan
• Primary Examiner(s): Donovan; Lincoln
• Assistant Examiner(s): ROJAS, DANIEL E
• Application Number:
  US11/760,782
• Publication Number:
  US 20070285138A1
• Time in Patent Office: 1,003 Days
• Field of Search: 327/158
• US Class Current: 327/158
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled

Abstract

A Delay Locked Loop (DLL) and method for generating multiple equally spaced phases over a wide frequency range is disclosed. The DLL includes a delay line, and a control module. The delay line receives a reference clock signal and outputs a final delay clock signal in response to the reference clock signal. The delay line includes a plurality of delay cells connected in series. The plurality of delay cells generate a plurality of delay clock signals having equally spaced phases. The control module generates a phase control signal based on counting a number of pulses of the reference clock signal that are input to the delay line before occurrence of a first corresponding pulse of the final delay clock signal.

Claims

1. A Delay Locked Loop (DLL) with equally spaced phases over a wide frequency range, the DLL comprising:

a delay line for receiving a reference clock signal and outputting a final delay clock signal in response to the reference clock signal, wherein the delay line includes a plurality of delay cells connected in series, the plurality of delay cells generating a plurality of delay clock signals having equally spaced phases;

a control module coupled to the delay line, for generating a phase control signal based on counting a number of pulses of the reference clock signal that are input to the delay line before occurrence of a first corresponding pulse of the final delay clock signal, the control module comprising;

a calibration module for generating a co-prime number with respect to the plurality of delay clock signals, wherein the co-prime number is generated based on counting the number of pulses of the reference clock signal, the calibration module comprising;

a counter for counting the number of pulses of the reference clock signal;

a decoder coupled to the counter, for generating the co-prime number by decoding a count of the number of pulses of the reference clock signal;

a masking module for masking edges of the reference clock signal and the final delay clock signal; and

a phase control module coupled to the calibration module, for generating the phase control signal based on a value of the co-prime number.

2. The DLL of claim 1, wherein the masking module masks the edges of the reference clock signal and the final delay clock signal for a pre-defined time interval.

3. The DLL of claim 1, wherein the masking module masks the edges of the reference clock signal and the final delay clock signal for a pre-defined number of edges of the reference clock signal and the final delay clock signal.

4. The DLL of claim 1, wherein the masking module comprises:

a first mask module for masking the edges of the reference clock signal, wherein the first mask module generates a ‘

start_count’

signal on masking the edges of the reference clock signal; and

a second mask module for masking the edges of the final delay clock signal, wherein the second mask module generates a ‘

stop_count’

signal on occurrence of the first corresponding pulse of the final delay clock signal.

5. The DLL of claim 4, wherein the counter counts the number of pulses of the reference clock signal based on the start_count signal and the stop_count signal.

6. A Delay Locked Loop (DLL) with equally spaced phases over a wide frequency range, the DLL comprising:

a calibration module that generates a number, wherein the number and a count of a delay clock signal for an interval of time are co-prime to each other;

a phase control module responsive to a reference clock signal, the delay clock signal, and the number, and to generate a phase control signal based on a value of the number, the phase control module comprising;

a divider module for dividing frequency of the reference clock signal and a final delay clock signal by the number;

a Phase Frequency Detector (PFD) coupled to the divider module, for comparing phases of the reference clock signal and the final delay clock signal; and

a charge pump coupled to the PFD, for generating the phase control signal based on comparing the phases of the reference clock signal and the final delay clock signal.

7. The DLL of claim 6, wherein the divider module comprises:

a first divider circuit for dividing the frequency of the reference clock signal by the number; and

a second divider circuit for dividing the frequency of the final delay clock signal by the number.

8. A Delay Locked Loop (DLL) with equally spaced phases over a wide frequency range, wherein the DLL receives a reference clock signal and outputs a plurality of delay clock signals such that a phase difference between any two adjacent delay clock signals of the plurality of delay clock signals is equal, the plurality of delay clock signals including a final delay clock signal, the DLL comprising:

a masking module for masking a pre-defined number of edges of the reference clock signal and the final delay clock signal, and generating a start_count signal and a stop_count signal upon masking the pre-defined number of edges of the reference clock signal and the final delay clock signal respectively;

a counter coupled to the masking module, for generating a count of a number of pulses of the reference clock signal that are input to the delay line between inputting a pulse of the reference clock signal to the delay line and occurrence of a corresponding pulse of the final delay clock signal;

a decoder coupled to the counter, for decoding the count to generate a co-prime number with respect to a number of delay clock signals in the plurality of delay clock signals;

a divider module coupled to the decoder, for receiving a value of the co-prime number, and dividing frequencies of the reference clock signal and the final delay clock signal by the co-prime number to generate a reference phase signal and a delay phase signal respectively;

a Phase Frequency Detector (PFD) coupled to the divider module, for comparing the reference phase signal and the delay phase signal in terms of phase;

a charge pump coupled to the PFD, for generating a phase control signal based on comparing the reference phase signal and the delay phase signal; and

a delay line coupled to the charge pump, wherein the delay line includes a plurality of delay cells connected in series, the plurality of delay cells generating the plurality of delay clock signals on receiving the phase control signal.

9. The DLL of claim 8, wherein the masking module comprises:

a first mask module for masking the pre-defined number of edges of the reference clock signal; and

a second mask module for masking the pre-defined number of edges of the final delay clock signal.

10. The DLL of claim 8, wherein the divider module comprises:

a first divider circuit for dividing the frequency of the reference clock signal by the co-prime number to generate the reference phase signal; and

a second divider circuit for dividing the frequency of the final delay clock signal by the co-prime number to generate the delay phase signal.

11. A method for generating a plurality of equal-spaced phases with a wide frequency range using a Delay Locked Loop (DLL), the DLL including a plurality of delay cells connected in series, the plurality of delay cells generating a plurality of delay clock signals in response to a reference clock signal, the plurality of delay clock signals including a final delay clock signal, the method comprising:

generating a number, wherein the number and a count of a delay clock signal for an interval of time are co-prime to each other;

dividing a frequency of the reference clock signal and the final delay clock signal by the number to generate a reference phase signal and a delay phase signal respectively;

comparing phases of the reference phase signal and the delay phase signal;

generating a phase control signal based on comparing the phases; and

controlling a phase difference between any two adjacent delay clock signals of the plurality of delay clock signals through the phase control signal for generating the plurality of equal-spaced phases.

12. The method of claim 11, wherein generating the number comprises:

generating a count of a number of pulses of the reference clock signal that are input to the plurality of delay cells before occurrence of a first corresponding pulse of the final delay clock signal;

decoding the count to generate a count value;

outputting the count value when the count is co-prime to the count of the final delay clock signal; and

outputting a next number greater than the count value, wherein the next number is co-prime to the number of delay clock signals in the plurality of delay clock signals when the count is not co-prime to the number of delay clock signals.

13. The method of claim 11, wherein generating the number further comprises masking edges of the reference clock signal and the final delay clock signal.