Semiconductor device

• US 7,675,358 B2
• Filed: 10/05/2005
• Issued: 03/09/2010
• Est. Priority Date: 10/07/2004
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Atsumi, Tomoaki
• Primary Examiner(s): Pascal; Robert
• Assistant Examiner(s): Goodley; James E
• Application Number:
  US11/576,585
• Publication Number:
  US 20080088367A1
• Time in Patent Office: 1,616 Days
• Field of Search: 340/572.1, 340/10.1, 340/10.41, 329/312, 329/348
• US Class Current: 329/348
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

The invention provides a semiconductor device that generates a clock signal with a fixed pulse width from a carrier. The invention also provides a semiconductor device where data can be obtained accurately from a carrier using a clock signal with a fixed pulse width. Further, the invention provides a semiconductor device that has a simpler circuit configuration and a smaller scale, and consumes less power as compared to the PLL circuit. According to the invention, a signal obtained by dividing a carrier including 100% modulation is not used as a clock signal, and a correction circuit is used to generate a clock signal using a demodulated signal and a signal obtained by dividing the carrier including 100% modulation. According to the invention having such a configuration, a clock signal with a fixed pulse width can be generated.

Claims

1. A semiconductor device comprising:

a divider circuit for dividing a carrier;

a demodulated signal separation circuit for generating a plurality of demodulated signals using a demodulated signal demodulated from the carrier; and

a correction circuit for generating a clock signal using an output signal from the divider circuit and the plurality of demodulated signals supplied from the demodulated signal separation circuit.

6. The semiconductor device according to claim 1, wherein a plurality of D-type flip flops are used for the divider circuit.

7. The semiconductor device according to claim 1, wherein a plurality of D-type flip flops are used for the divider circuit;

and

wherein the last stage D-type flip flop is a D-type flip flop having an asynchronous negative reset function.

8. The semiconductor device according to claim 1, wherein an EXNOR circuit is used for the correction circuit.

9. The semiconductor device according to claim 1, wherein an antenna for receiving the carrier and a resonant capacitor are provided.

22. The semiconductor device according to claim 1, wherein the carrier includes 100% modulation defined by ISO/IEC 15693, 100% modulation defined by ISO/IEC 14443 (TYPE-A), 100% modulation defined by ISO/IEC 18000-3, or modulation with an amplitude 5% or less of an amplitude in a state where a signal is not modulated.

2. A semiconductor device comprising:

a divider circuit for dividing a carrier;

a demodulation circuit for generating a demodulated signal using the carrier;

a demodulated signal separation circuit for generating a plurality of demodulated signals using the demodulated signal; and

a correction circuit for generating a clock signal using an output signal from the divider circuit and the plurality of demodulated signals supplied from the demodulated signal separation circuit.

10. The semiconductor device according to claim 2, wherein a plurality of D-type flip flops are used for the divider circuit.

11. The semiconductor device according to claim 2, wherein a plurality of D-type flip flops are used for the divider circuit;

and

wherein the last stage D-type flip flop is a D-type flip flop having an asynchronous negative reset function.

12. The semiconductor device according to claim 2, wherein an EXNOR circuit is used for the correction circuit.

13. The semiconductor device according to claim 2, wherein an antenna for receiving the carrier and a resonant capacitor are provided.

23. The semiconductor device according to claim 2, wherein the carrier includes 100% modulation defined by ISO/IEC 15693, 100% modulation defined by ISO/IEC 14443 (TYPE-A), 100% modulation defined by ISO/IEC 18000-3, or modulation with an amplitude 5% or less of an amplitude in a state where a signal is not modulated.

3. A semiconductor device comprising:

a divider circuit for dividing a carrier;

a demodulation circuit for generating a first demodulated signal using the carrier;

a demodulated signal separation circuit for generating from the first demodulated signal a second demodulated signal obtained by amplifying the first demodulated signal, a third demodulated signal obtained by separating only a first pulse from the first demodulated signal, and a fourth demodulated signal obtained by separating pulses other than the first pulse from the first demodulated signal; and

a correction circuit for generating a clock signal using an output signal from the divider circuit, the third demodulated signal and the fourth demodulated signal.

14. The semiconductor device according to claim 3, wherein a plurality of D-type flip flops are used for the divider circuit.

15. The semiconductor device according to claim 3, wherein a plurality of D-type flip flops are used for the divider circuit;

and

wherein the last stage D-type flip flop is a D-type flip flop having an asynchronous negative reset function.

16. The semiconductor device according to claim 3, wherein an EXNOR circuit is used for the correction circuit.

17. The semiconductor device according to claim 3, wherein an antenna for receiving the carrier and a resonant capacitor are provided.

24. The semiconductor device according to claim 3, wherein the carrier includes 100% modulation defined by ISO/IEC 15693, 100% modulation defined by ISO/IEC 14443 (TYPE-A), 100% modulation defined by ISO/IEC 18000-3, or modulation with an amplitude 5% or less of an amplitude in a state where a signal is not modulated.

4. A semiconductor device comprising:

a divider circuit for dividing a carrier;

a demodulation circuit for generating a first demodulated signal using the carrier;

a demodulated signal separation circuit for generating from the first demodulated signal a second demodulated signal obtained by amplifying the first demodulated signal, a third demodulated signal obtained by separating only a first pulse from the first demodulated signal, and a fourth demodulated signal obtained by separating pulses other than the first pulse from the first demodulated signal;

a demodulated signal generating circuit for generating from the third demodulated signal and the fourth demodulated signal a fifth demodulated signal obtained by delaying the fourth demodulated signal; and

a correction circuit for generating a clock signal using an output signal from the divider circuit and the fifth demodulated signal.

5. The semiconductor device according to claim 4, wherein a D-type flip flop is used for the demodulated signal generating circuit.

18. The semiconductor device according to claim 4, wherein a plurality of D-type flip flops are used for the divider circuit.

19. The semiconductor device according to claim 4, wherein a plurality of D-type flip flops are used for the divider circuit;

and

wherein the last stage D-type flip flop is a D-type flip flop having an asynchronous negative reset function.

20. The semiconductor device according to claim 4, wherein an EXNOR circuit is used for the correction circuit.

21. The semiconductor device according to claim 4, wherein an antenna for receiving the carrier and a resonant capacitor are provided.

25. The semiconductor device according to claim 4, wherein the carrier includes 100% modulation defined by ISO/IEC 15693, 100% modulation defined by ISO/IEC 14443 (TYPE-A), 100% modulation defined by ISO/IEC 18000-3, or modulation with an amplitude 5% or less of an amplitude in a state where a signal is not modulated.