Memory circuit, display device and electronic equipment each comprising the same
First Claim
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1. An SRAM circuit comprising:
- a word line, a plurality of memory cells, and a driver circuit for driving the word line,wherein each of the plurality of memory cells includes a switching transistor having a gate which is electrically connected to the word line,wherein the driver circuit includes a first level shift circuit configured to output a first signal to the word line and a second level shift circuit configured to output a second signal to the word line, andwherein an amplitude of the first signal is larger than an amplitude of the second signal.
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Abstract
A memory circuit using a thin film transistor has been problems such as the drop in yield and the decrease in speed of response of the memory circuit due to variations in transistors. The purpose of the invention is to improve the yield and speed of the response of a memory cell by driving a word line by a voltage which is different from the logical amplitude of the memory cell. The invention is applicable to an SRAM, a DRAM, a mask ROM, and the like. A memory circuit of the invention is formed integrally with a display device for realizing a multi-functional display device.
22 Citations
58 Claims
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1. An SRAM circuit comprising:
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a word line, a plurality of memory cells, and a driver circuit for driving the word line, wherein each of the plurality of memory cells includes a switching transistor having a gate which is electrically connected to the word line, wherein the driver circuit includes a first level shift circuit configured to output a first signal to the word line and a second level shift circuit configured to output a second signal to the word line, and wherein an amplitude of the first signal is larger than an amplitude of the second signal. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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2. An SRAM circuit comprising:
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a word line, a plurality of memory cells, and a driver circuit connected to the word line, wherein each of the plurality of memory cells includes a switching transistor having a gate which is electrically connected to the word line, wherein the driver circuit includes a first level shift circuit configured to output a first signal to the word line and a second level shift circuit configured to output a second signal to the word line, and wherein an amplitude of the first signal is larger than an output amplitude of the memory cell. - View Dependent Claims (15, 20, 25, 30, 35, 40)
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3. An SRAM circuit comprising:
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a word line, a plurality of memory cells, and a driver circuit connected to the word line, wherein each of the plurality of memory cells includes a switching transistor having a gate which is electrically connected to the word line, wherein the driver circuit includes a first level shift circuit configured to output a first signal to the word line and a second level shift circuit configured to output a second signal to the word line, and wherein an amplitude of the first signal is smaller than an output amplitude of the memory cell. - View Dependent Claims (16, 21, 26, 31, 36, 41)
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4. An SRAM circuit comprising:
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a word line, a plurality of memory cells, and a driver circuit connected to the word line, wherein each of the plurality of memory cells includes a switching transistor having a gate which is electrically connected to the word line, wherein the driver circuit includes a variable level shift circuit for changing a potential of a signal which turns on the switching transistor so that a current capability of the switching transistor is changed, and wherein the variable level shift circuit has a first switch and a second switch for varying an output amplitude. - View Dependent Claims (6, 17, 22, 27, 32, 37, 42)
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5. An SRAM circuit comprising:
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a word line, a plurality of memory cells, and a driver circuit connected to the word line, wherein each of the plurality of memory cells includes a switching transistor having a gate which is electrically connected to the word line, wherein the driver circuit includes a variable level shift circuit for changing a potential of a signal which turns on the switching transistor so that a current capability of the switching transistor is changed, and wherein the variable level shift circuit has a first switch and a second switch for varying an output amplitude when writing and reading. - View Dependent Claims (14, 18, 23, 28, 33, 38, 43)
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7. An SRAM circuit comprising:
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a word line, a plurality of memory cells, and a driver circuit connected to the word line, wherein each of the plurality of memory cells includes a switching transistor having a gate which is electrically connected to the word line, wherein the driver circuit includes a variable level shift circuit for changing a potential of a signal which turns on the switching transistor so that a current capability of the switching transistor is changed, wherein an output amplitude of the variable level shift circuit in writing is larger than an output amplitude in reading wherein the variable level shift circuit has a first switch and a second switch for varying the output amplitude reading. - View Dependent Claims (19, 24, 29, 34, 39, 44)
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45. An SRAM circuit comprising:
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a word line; a memory cell including a switching transistor, a first inverter and a second inverter; and a driver circuit for driving the word line and including a variable level shift circuit having an output terminal electrically connected to the word line, wherein an input terminal of the first inverter is electrically connected to an output terminal of the second inverter, and an input terminal of the second inverter is electrically connected to an output terminal of the first inverter, wherein a gate of the switching transistor is electrically connected to the word line, and one of a source and a drain of the switching transistor is electrically connected to the input terminal of the first inverter, wherein the variable level shift circuit is configured to output a first signal to the word line for performing a writing operation and a second signal to the word line for performing a reading operation, an amplitude of the first signal is larger than an amplitude of the second signal, and wherein the variable level shift circuit has a first switch and a second switch for varying the output amplitude. - View Dependent Claims (46, 47, 48, 49, 50, 51)
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52. A driving method of an SRAM circuit comprising a word line, a memory cell including a switching transistor, a first inverter and a second inverter and a driver circuit for driving the word line including a variable level shift circuit, the method comprising:
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outputting a first signal from the variable level shift circuit to the word line for performing a writing operation; and outputting a second signal from the variable level shift circuit into the word line for performing a reading operation, wherein an amplitude of the first signal is larger than an amplitude of the second signal, and wherein the variable level shift circuit has a first switch and a second switch for varying the output amplitude. - View Dependent Claims (53, 54, 55, 56, 57, 58)
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Specification
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Current AssigneeSemiconductor Energy Laboratory Co., Ltd.
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Original AssigneeSemiconductor Energy Laboratory Co., Ltd.
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InventorsAtsumi, Tomoaki, Koyama, Jun
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Primary Examiner(s)Hjerpe; Richard
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Assistant Examiner(s)Abdin; Shaheda A
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Application NumberUS10/890,110Publication NumberTime in Patent Office2,064 DaysField of Search345/205, 345/77, 365/185.01, 365/189.07, 365/201, 365/203, 365/202, 365/206US Class Current345/205CPC Class CodesG11C 11/4085 Word line control circuits,...G11C 11/418 Address circuitsG11C 8/08 Word line control circuits,...
