Memory device, method for operating a memory device, and apparatus for use with a memory device

• US 7,675,781 B2
• Filed: 12/01/2006
• Issued: 03/09/2010
• Est. Priority Date: 12/01/2006
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Deml, Christoph, Paparisto, Edvin
• Primary Examiner(s): Ho; Hoai V
• Assistant Examiner(s): Hidalgo; Fernando N
• Application Number:
  US11/607,354
• Publication Number:
  US 20080133849A1
• Time in Patent Office: 1,194 Days
• Field of Search: 365/185.21, 365/185.25, 365/189.07, 365/189.09
• US Class Current: 365/185.21
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

A memory device, including a non-volatile memory device, a method for operating a memory device, and an apparatus for use with a memory device is disclosed. In one embodiment, the memory device includes at least one evaluation circuit for amplifying a signal resulting from the reading of a memory cell, and a device for precharging an output of the evaluation circuit to a predetermined voltage level.

Claims

1. A memory device, comprising:

a bit line connected to a memory cell;

at least one evaluation circuit configured to amplify a signal resulting from the reading of the memory cell, the evaluation circuit comprising;

at least one current mirror device with a first and a second transistor, a gate of the first transistor coupled to a source or a drain of the first transistor; and

an output of the evaluation circuit coupled to a source or a drain of the second transistor; and

a device configured to precharge the output of the evaluation circuit to a selected voltage level based on a voltage level of the bit line as compared to a predetermined voltage level.

2. The memory device of claim 1, wherein the output of the evaluation circuit is connected to an inverter.

3. The memory device of claim 1, wherein an input of the evaluation circuit is connectable with the bit line connectable with the memory cell.

4. The memory device of claim 3, further comprising a device for precharging the bit line to a further predetermined voltage level.

5. The memory device of claim 1, wherein the evaluation circuit further comprises a second current mirror device with a third and fourth transistor, wherein:

a gate of the second transistor is coupled to the source or the drain of the first transistor;

the output of the evaluation circuit is coupled to a source or a drain of the fourth transistor;

a gate of the fourth transistor is coupled to a source or a drain of the third transistor; and

the source or the drain of the third transistor is coupled to a reference voltage source.

16. The memory device of claim 1, wherein the memory cell is a non-volatile memory cell.

17. The memory device of claim 16, wherein the memory cell is a PROM, EPROM, EEPROM, flash, or OTP memory cell.

18. A chip with a memory device according to claim 1.

6. A memory device, comprising:

a bit line connected to a memory cell;

at least one evaluation circuit configured to amplify a signal resulting from the reading of the memory cell, the evaluation circuit comprising;

at least one current mirror device having a first and a second transistor, a gate of the first transistor coupled to a source or a drain of the first transistor; and

an output of the evaluation circuit coupled to a source or a drain of the second transistor; and

a device configured to precharge the output of the evaluation circuit to a selected voltage level based on a voltage level of the bit line as compared to a predetermined voltage level;

wherein the device for precharging the output comprises a precharge transistor for connecting/disconnecting a voltage source having the selected voltage level to/from the output of the evaluation circuit based on the voltage level of the bit line as compared to the predetermined voltage level.

7. The memory device of claim 6, additionally comprising:

a control device for controlling the precharge transistor such that in a first phase of the reading of the memory cell the output of the evaluation circuit is connected to the voltage source, and in a second phase of the reading of the memory cell the output of the evaluation circuit is disconnected from the voltage source.

8. The memory device of claim 7, wherein an input of the evaluation circuit is connectable with the bit line connectable with the memory cell, and wherein the control device compares the voltage level on the bit line with the predetermined voltage level.

9. The memory device of claim 8, wherein the output of the evaluation circuit is connected to the voltage source when the voltage level on the bit line is less than the predetermined voltage level, and the output of the evaluation circuit is disconnected from the voltage source when the voltage level on the bit line is at least equal to the predetermined voltage level.

10. The memory device of claim 8, wherein the output of the evaluation circuit is connected with an output device, and wherein the output device is deactivated when the voltage level on the bit line is less than the predetermined voltage level, and the output device is activated when the voltage level on the bit line is at least equal to the predetermined voltage level.

11. The memory device of claim 10, wherein the output device comprises an inverter.

12. The memory device of claim 8, wherein the control device comprises an operational amplifier.

13. The memory device of claim 9, further comprising:

a device for precharging the bit line to a further predetermined voltage level, wherein the further predetermined voltage level is bigger, than the predetermined voltage level.

14. The memory device of claim 13, wherein the device for precharging the bit line comprises an operational amplifier.

15. The memory device of claim 14, wherein the device for precharging the bit line comprises a transistor, coupled to the output of the operational amplifier.

19. An apparatus for use with a memory device, comprising:

a sense amplifier comprising;

a first current mirror device with a first and a second transistor;

and a second current mirror device with a third and a fourth transistor, wherein a gate of the first transistor is coupled to a source-drain path of the second transistor, and a gate of the third transistor is coupled to a source-drain path of the fourth transistor, and an output of the sense amplifier is coupled to a source-drain path of the first transistor of the first current mirror device, and to a source-drain path of the third transistor of the second current mirror device; and

a device for precharging the output of the sense amplifier to a selected voltage level based on a voltage level of a bit line of a memory cell coupled to the sense amplifier as compared to a predetermined voltage level.

20. The apparatus of claim 19, wherein the device comprises:

a switch configured to connect the output of the sense amplifier to a voltage source at the selected voltage level in a first phase of the reading of the memory cell, and to disconnect the output of the sense amplifier from the voltage source in a second phase of the reading of the memory cell.

21. The apparatus of claim 20, wherein the switch comprises a transistor.

22. A method for operating a memory device, the method comprising:

amplifying a signal resulting from the reading of a memory cell using an evaluation circuit comprising at least one current mirror device having a first and a second transistor, a gate of the first transistor coupled to a source or a drain of the first transistor, and an output of the evaluation circuit coupled to a source or a drain of the second transistor; and

precharging the output of the evaluation circuit to a selected voltage level based on a voltage level of a bit line connected to the memory cell as compared to a predetermined voltage level using a device coupled to the source or the drain of the second transistor.

23. The method of claim 22, comprising:

connecting the output of the evaluation circuit to a voltage source having the selected voltage level in a first phase of the reading of the memory cell to precharge the output to the selected voltage level; and

disconnecting the output of the evaluation circuit from the voltage source in a second phase of the reading of the memory cell.

24. The method of claim 23, wherein the memory device additionally comprises an output circuit coupled to the output of the evaluation circuit, the method comprising:

enabling or disabling the output circuit, or driving an output of the output circuit to a predetermined state.

25. A memory device, comprising:

a bit line connected to a memory cell;

at least one evaluation circuit means for amplifying a signal resulting from the reading of the memory cell comprising;

at least one current mirror device with a first and a second transistor, a gate of the first transistor coupled to a source or a drain of the first transistor; and

an output of the evaluation circuit means which is coupled to a source or a drain of the second transistor; and

means for precharging the output coupled to the source or the drain of the second transistor to a selected voltage level depending on a voltage level of the bit line as compared to a predetermined voltage level.