Method, system and circuit for programming a non-volatile memory array

• US 7,675,782 B2
• Filed: 10/17/2006
• Issued: 03/09/2010
• Est. Priority Date: 10/29/2002
• Status: Expired due to Fees

• Current Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Polansky, Yan, Cohen, Guy
• Primary Examiner(s): Nguyen; Dang T
• Application Number:
  US11/581,449
• Publication Number:
  US 20070115726A1
• Time in Patent Office: 1,239 Days
• Field of Search: 365/185.24, 365/185.19, 365/185.33, 365/185.25, 365/185.28, 365/189.03
• US Class Current: 365/185.24
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3468 Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing

Abstract

The present invention is a multi-phase method, circuit and system for programming non-volatile memory (“NVM”) cells in an NVM array. The present invention may include a controller to determine when, during a first programming phase, one or more NVM cells of a first set of cells reaches or exceeds a first intermediate voltage, and to cause a charge pump circuit to apply to a terminal of the one or more cells in the first set second phase programming pulses to induce relatively greater threshold voltage changes in cells having less stored charge than in cells having relatively more stored charge.

Claims

1. A method of programming an array of non-volatile memory (“

NVM”

) cells, said method comprising;

substantially concurrently applying different programming pulses to a first set and a second set of NVM cells, wherein the first set of NVM cells is associated with a first target threshold voltage and the second set of NVM cells is associated with a second target threshold voltage, and further comprising;

upon one or more NVM cells of the first or second sets of cells reaching or exceeding an intermediate threshold voltage level associated with either the first or second set, applying to a terminal of one or more cells in either the first or second set second phase programming pulses adapted to induce relatively greater threshold voltage changes in cells having less stored charge than in cells having relatively more stored charge.

2. The method according to claim 1, wherein applying second phase programming pulses comprises applying to a terminal of the NVM cell programming pulses of substantially fixed voltage in concert with gate pulses of incrementally increasing voltage.

3. The method according to the claim 2, wherein applying to a terminals of the one or more cells of the first set second phase programming pulses of substantially fixed voltage in concert with gate pulses of incrementally increasing voltage is repeated until one or more of the cells of the first set reaches a first target threshold voltage level.

4. The method according to claim 1, further comprising substantially concurrently applying programming pulses to a third set of NVM cells, wherein the third set of NVM cells is intended to be programmed to a threshold voltage different from that of the first and second sets.

5. A System for programming an array of non-volatile memory (“

NVM”

) cells, said system comprising;

a controller adapted to cause a charge pump circuit to substantially concurrently apply different programming pulses to a first set and a second set of NVM cells, wherein the first set of NVM cells is associated with a first target threshold voltage and the second set of NVM cells is associated with a second target threshold voltage, and wherein the controller is further adapted to determine when one or more NVM cells of the first or second sets of cells reaches or exceeds an intermediate threshold voltage level associated with either the first or second set and to cause said charge pump circuit to apply to a terminal of one or more cells in either the first or second set second phase programming pulses adapted to induce relatively greater threshold voltage changes in cells having less stored charge than in cells having relatively more stored charge.

6. The system according to claim 5, wherein said controller is adapted to cause said charge pump circuit to apply second phase programming pulses by applying to a terminal of the NVM cell programming pulses of substantially fixed voltage in concert with gate pulses of incrementally increasing voltage.

7. The system according to the claim 6, wherein said controller is adapted to cause said charge pump to apply to a terminals of the one or more cells of the first set second phase programming pulses of substantially fixed voltage in concert with gate pulses of incrementally increasing voltage is repeated until one or more of the cells of the first set reaches a first target threshold voltage level.

8. The system according to claim 5, wherein said controller is further adapted to cause a charge pump circuit to substantially concurrently apply programming pulses to a third set of NVM cells, wherein the third set of NVM cells is intended to be programmed to a threshold voltage different from that of the first and second sets.

9. A non-volatile memory (“

NVM”

) device comprising;

a controller adapted to cause a charge pump circuit to substantially concurrently apply different programming pulses to a first set and a second set of NVM cells, wherein the first set of NVM cells is associated with a first target threshold voltage and the second set of NVM cells is associated with a second target threshold voltage, and wherein the controller is further adapted to determine when one or more NVM cells of the first or second sets of cells reaches or exceeds an intermediate threshold voltage level associated with either the first or second set and to cause said charge pump circuit to apply to a terminal of one or more cells in either the first or second set second phase programming pulses adapted to induce relatively greater threshold voltage changes in cells having less stored charge than in cells having relatively more stored charge.

10. The device according to claim 9, wherein said controller is adapted to cause said charge pump circuit to apply second phase programming pulses by applying to a terminal of the NVM cell programming pulses of substantially fixed voltage in concert with gate pulses of incrementally increasing voltage.

11. The device according to the claim 10, wherein said controller is adapted to cause said charge pump to apply to a terminals of the one or more cells of the first set second phase programming pulses of substantially fixed voltage in concert with gate pulses of incrementally increasing voltage is repeated until one or more of the cells of the first set reaches a first target threshold voltage level.

12. The device according to claim 11, wherein said controller is further adapted to cause a charge pump circuit to substantially concurrently apply programming pulses to a third set of NVM cells, wherein the third set of NVM cells is intended to be programmed to a threshold voltage different from that of the first and second sets.