Methods and systems for utilizing design data in combination with inspection data

• US 7,676,077 B2
• Filed: 11/20/2006
• Issued: 03/09/2010
• Est. Priority Date: 11/18/2005
• Status: Active Grant

• Current Assignee: Kla-Tencor Technologies Corporation (KLA Corporation)
• Original Assignee: Kla-Tencor Technologies Corporation (KLA Corporation)
• Inventors: Kulkarni, Ashok, Duffy, Brian, Maayah, Kais, Rouse, Gordon
• Primary Examiner(s): Le; Brian Q
• Application Number:
  US11/561,735
• Publication Number:
  US 20070156379A1
• Time in Patent Office: 1,205 Days
• Field of Search: 382/144, 382/145, 382/151, 382/187, 382/294
• US Class Current: 382/144
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: H01L 21/67005 Apparatus not specifically provided for elsewhere processes per se H01L21/30, H01L21/46, H01L23/00; simple temporary support means, e.g. using adhesives, electric or magnetic means H01L21/68, H01L21/302

Abstract

Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for determining a position of inspection data in design data space includes aligning data acquired by an inspection system for alignment sites on a wafer with data for predetermined alignment sites. The method also includes determining positions of the alignment sites on the wafer in design data space based on positions of the predetermined alignment sites in the design data space. In addition, the method includes determining a position of inspection data acquired for the wafer by the inspection system in the design data space based on the positions of the alignment sites on the wafer in the design data space. In one embodiment, the position of the inspection data is determined with sub-pixel accuracy.

Claims

1. A computer-implemented method for determining a position of inspection data in design data space, comprising:

using a computer system to performing the following steps;

aligning data acquired by an inspection system for alignment sites on a wafer with data for predetermined alignment sites;

determining positions of the alignment sites on the wafer in design data space based on positions of the predetermined alignment sites in the design data space;

determining a position of inspection data acquired for the wafer by the inspection system in the design data space based on the positions of the alignment sites on the wafer in the design data space; and

determining a sensitivity for detecting defects on different portions of the wafer based on the position of the inspection data in the design data space, one or more attributes of design data in the design data space, and one or more attributes of the inspection data, wherein the one or more attributes of the inspection data comprise one or more image noise attributes, if one or more defects were detected in the different portions, or some combination thereof.

2. The method of claim 1, wherein the position of the inspection data is determined with sub-pixel accuracy.

3. The method of claim 1, wherein the data for the predetermined alignment sites comprises the design data stored in a data structure.

4. The method of claim 1, wherein the data for the predetermined alignment sites comprises one or more simulated images illustrating how the predetermined alignment sites will be printed on the wafer.

5. The method of claim 1, wherein the data for the predetermined alignment sites comprises one or more attributes of the predetermined alignment sites, wherein the data for the alignment sites comprises one or more attributes of the alignment sites, and wherein said aligning comprises aligning the one or more attributes of the predetermined alignment sites to the one or more attributes of the alignment sites.

6. The method of claim 5, wherein the one or more attributes of the predetermined alignment sites comprise centroids of the predetermined alignment sites, and wherein the one or more attributes of the alignment, sites comprise centroids of the alignment sites.

7. The method of claim 1, wherein the data for the predetermined alignment sites comprises data acquired by the inspection system that has been aligned to the design data stored in a data structure.

8. The method of claim 1, wherein the data for the predetermined alignment sites comprises at least a portion of a standard reference die image that has been aligned to design coordinates in the design data space.

9. The method of claim 1, wherein the predetermined alignment sites comprise at least one alignment feature having one or more attributes that are unique in the x and y directions or at least two alignment features, wherein a first of the at least two alignment features has one or more attributes that are unique in the x direction, arid wherein a second of the at least two alignment features has one or more attributes that are unique in the y direction.

10. The method of claim 1, further comprising selecting the predetermined alignment sites using the inspection system.

11. The method of claim 10, wherein an imaging mode of the inspection system used for said selecting is different than an imaging mode of the inspection system used to acquire the inspection data.

12. The method of claim 1, wherein determining the positions of the alignment sites is performed before inspection of the wafer, arid wherein determining the position of the inspection data is performed during the inspection of the wafer.

13. The method of claim 1, wherein determining the position of the inspection data is performed subsequent to inspection of the wafer, and wherein determining the position of the inspection data is performed for portions of the inspection data corresponding to defects detected on the wafer arid riot for portions of the inspection data that do not correspond to the defects.

14. The method of claim 1, wherein the data for the alignment sites is within a swath of the inspection data, and wherein determining the position of the inspection data comprises determining the position of the swath in the design data space based on the positions of the alignment sites and determining the position of an additional swath of the inspection data in the design data space based on the position of the swath.

15. The method of claim 1, wherein the one or more attributes of the design data are selected based on one or more attributes of previously acquired inspection data for the wafer, other wafers, or some combination thereof for the design data, different design data, or some combination thereof for a process layer for which the inspection data for the wafer was acquired, for different process layers, or some combination thereof.

16. The method of claim 1, wherein the one or more attributes of the design data are selected based on yield criticality of defects previously detected in the different portions, fault probability of the defects previously detected in the different portions, or some combination thereof.

17. The method of claim 1, wherein determining the sensitivity comprises determining the sensitivity for detecting the defects on the different portions of the wafer based on the position of the inspection data in the design data space and context map, wherein the context map comprises values for the one or more attributes of the design data across the design data space.

18. The method of claim 17, wherein determining the sensitivity further comprises determining sensitivity thresholds used with the inspection data to detect the defects on the different portions of the wafer.

19. The method of claim 17, wherein determining the sensitivity is performed by the inspection system during inspection of the wafer.

20. The method of claim 17, wherein determining the sensitivity is performed after acquisition of the inspection data for the wafer has been completed.

21. The method of claim 1, further comprising altering one or more parameters for detecting the defects on the wafer based on one or more attributes of schematic data for a design of a device being fabricated on the wafer, One or more attributes of expected electrical behavior of a physical layout for the device, or some combination thereof.

22. The method of claim 1, further comprising altering one or more parameters for detecting the defects on the wafer using the inspection data based on one or more parameters of an electrical test process to be performed on the wafer.

23. The method of claim 1, further comprising altering one or more parameters of an electrical test process to be performed on the wafer based on defects detected on the wafer using the inspection data.

24. The method of claim 1, further comprising periodically altering one or more parameters of an inspection process performed by the inspection system based on results of one or more steps of the method using a feedback control technique.

25. The method of claim 1, further comprising automatically altering one or more parameters of an inspection process performed by the inspection system based on results of one or more steps of the method using a feedback control technique.

26. The method of claim 1, further comprising generating a knowledge base using results of one or more steps of the method and generating an inspection process performed by the inspection system using the knowledge base.

27. The method of claim 1, further comprising classifying defects detected on the different portions of the wafer based on the positions of portions of the inspection data corresponding to the defects in the design data space and a context map, wherein the context map comprises values for the one or more attributes of the design data across the design data space.

28. The method of claim 27, wherein said classifying is performed by the inspection system during inspection on of the wafer.

29. The method of claim 27, wherein said classifying is performed after acquisition of the inspection data for the wafer has been completed.

30. The method of claim 1, wherein the inspection data comprises data for defects on the wafer, the method further comprising determining positions of the defects in the design data space based on the position of the inspection data in the design data space and determining if the defects are nuisance defects based on the positions of the defects in the design data space and one or more attributes of the design data in the design data space.

31. The method of claim 30, further comprising determining if the defects not determined to be nuisance defects are systematic or random defects based on the one or more attributes of the design data in the design data space.

32. The method of claim 1, wherein the inspection data is acquired for process window qualification.

33. The method of claim 1, wherein the inspection data comprises data for a defect on the wafer, the method further comprising classifying the defect based on the position of the inspection data in the design data space and one or more attributes of the design data in the design data space.

34. The method of claim 1, wherein the inspection data comprises data for defects on the wafer, the method further comprising binning the defects into groups based on the position of the inspection data in the design data space and one or more attributes of the design data in the design data space.

35. The method of claim 1 wherein the inspection data comprises data for defects on the wafer, the method further comprising binning the defects into groups based on the position of the inspection data in the design data space, one or more attributes of the design data in the design data space, and one or more attributes of reticle inspection data acquired for a reticle on which the design data is printed.

36. The method of claim 1, wherein the inspection data comprises data for defects on the wafer, the method further comprising binning the defects into groups based on the position of the inspection data in the design data space, one or more attributes of the design data in the design data space, and one or more attributes of the inspection data.

37. The method of claim 1, wherein the inspection data comprises data for defects on the wafer, the method further comprising binning the defects into groups based on the position of the inspection data in the design data space, one or more attributes of the design data in the design data space, one or more attributes of the inspection data, and one or more attributes of reticle inspection data acquired for a reticle on which the design data is printed.

38. The methods of claims 1, wherein the inspection data comprises data for defects on the wafer, the method further comprising binning the defects into groups based on the position of the inspection data in the design data space, one or more attributes of the design data in the design data space, one or more attributes of the inspection data, and one or more attributes of previously acquired inspection data for the wafer, other wafers or some combination thereof for the design data, different design data, or sonic combination thereof for a process layer for which the inspection data for the wafer was acquired, for different process layers, or some combination thereof.

39. The method of claim 1, wherein the inspection data comprises data for defects on the wafer, the method further comprising selecting at least a portion of the defects for review based on the position of the inspection data in the design data space and one or more attributes of the design data in the design data space.

40. The method of claim 1, wherein the inspection data comprises data for defects on the wafer, the method further comprising determining a sequence in which the defects are to be reviewed based on the position of the inspection data in the design data space and one or more attributes of the design data in the design data space.

41. The method of claim 1, wherein the inspection data comprises data for defects on the wafer, the method further comprising selecting at least a portion of the defects for review, wherein the at least the portion of the defects comprises at least one defect located within each portion of the design data in the design data space having different values of one or more attributes.

42. The method of claim 1, further comprising extracting one or more predetermined attributes of output from one or more detectors of the inspection system acquired for different portions of the wafer based on the position of the inspection data in the design data space and one or more attributes of the design data in the design data space.

43. The method of claim 42, wherein the one or more attributes of the design data are selected based on one or more attributes of previously acquired inspection data for the wafer, other wafers, or some combination thereof for the design data, different design data, or some combination thereof for a process layer for which the inspection data for the wafer was acquired, for different process layers, or some combination thereof.

44. The method of claim 1, further comprising extracting one or more predetermined attributes of output from one or more detectors of the inspection system acquired for different portions of the wafer based on the position of the inspection data in the design data space, one or more attributes of the design data in the design data space, and the one or more attributes of the inspection data.

45. The method of claim 1, further comprising determining a fault probability value for one or more defects detected on the wafer based on the position of the inspection data in the design data space and one or more attributes of the design data in the design data space.

46. The method of claim 1, further comprising determining coordinates of positions of defects detected on the wafer in the design data space based on the position of the inspection data in the design data space and translating the coordinates of the positions of the defects to design cell coordinates based on a floor plan for the design data.

47. The method of claim 46, further comprising determining different regions surrounding the defects using an overlay tolerance and performing defect repeater analysis using the regions for one or more cell types to determine if the one or more cell types are systematically defective cell types and to determine one or more locations of one or more systematically defective geometries within the systematically defective cell types.

48. The method of claim 47, further comprising determining if spatially systematic defects occur in the systematically defective cell types based on one or more attributes of the design data for cells, geometries, or some combination thereof located proximate to the systematically defective cell types.

49. The method of claim 1, further comprising determining a position of a defect detected on the wafer in the design data space based on the position of the inspection data in the design data space and determining values for one or more attributes of the design data corresponding to the position of the defect using a data structure in which predetermined values for the one or more attributes of the design data are stored as a function of position in the design data space.

50. The method of claim 1, wherein an image of a reticle generated by a reticle inspection system is used as the design data in the design data space, and wherein the reticle is used to print the design data on the wafer.

51. The method of claim 1, wherein a simulated image illustrating how a reticle image would be printed on the wafer is used as the design data in the design data space.

52. The method of claim 1, further comprising generating a context map for the design data in the design data space based on reticle inspection data acquired for a reticle used to print the design data on the wafer.

53. The method of claim 1, further comprising optimizing a wafer inspection process for determining printability of a reticle defect on the wafer using the position of the inspection data in the design data space and a context map.

54. The method of claim 1, further comprising detecting defects on the wafer using the inspection data and a standard reference die for standard reference die based inspection.

55. The method of claim 1, further comprising detecting defects on the wafer using the inspection data, a standard reference die, and a representation of wafer noise associated with the standard reference die in a perturbation matrix for standard reference die based inspection.

56. The method of claim 1, wherein the wafer and additional wafers are processed using wafer level process parameter modulation, and wherein the method further comprises detecting defects un the wafer and the additional wafers by comparing inspection data for die on the wafer and the additional wafers to a common standard reference die.

57. A system configured to determine a position of inspection data in design data space, comprising:

a storage medium comprising design data; and

a processor coupled to the storage medium, wherein the processor is configured to;

align data acquired by an inspection system for alignment sites on a wafer with data for predetermined alignment sites;

determine positions of the alignment sites on the wafer in design data based on positions of the predetermined alignment sites in the design data space;

determine a position of inspection data acquired for the wafer by the inspection system in the design data space based on the positions of the alignment sites on the wafer in the design data space; and

determine a sensitivity for detecting defects on different portions of the wafer based on the position of the inspection data in the design data space, one or more attributes of the design data in the design data space, and one or more attributes of the inspection data, wherein the one or more attributes of the inspection data comprise one or more image noise attributes, if one or more defects were detected in the different portions, or some combination thereof.

58. A system configured to determine a position of inspection data in design data space, comprising:

an inspection system configured to acquire data for alignment sites on a wafer and inspection data for the wafer;

a storage medium comprising design data; and

a processor coupled to the inspection system and the storage medium, wherein the processor is configured to;

align the data for the alignment sites on the wafer with data for predetermined alignment sites;

determine positions of the alignment sites on the wafer in design data space based on positions of the predetermined alignment sites in the design data space;

determine a position of the inspection data in the design data space based on the positions of the alignment sites on the wafer in the design day space; and

determine a sensitivity for detecting defects on different portions of the wafer based on the position of the inspection data in the design data space, one or more attributes of the design data in the design data space, and one or more attributes of the inspection data, wherein the one or more attributes of the inspection data comprise one or more image noise attributes, if one or more defects were detected in the different portions, or some combination thereof.