Method and apparatus for providing protected intellectual property
First Claim
1. A method for limiting operation of a protected intellectual property block on a programmable logic device (PLD), the method comprising:
- (a) identifying license information associated with the protected intellectual property block, wherein the license information indicates whether the protected intellectual property block should be implemented with a limit on run time during which the protected intellectual property block can operate on the programmable logic device;
(b) implementing the protected intellectual property block on the programmable logic device; and
(c) limiting the operation of the protected intellectual property block on the programmable logic device based on the license information by limiting operation of a portion of the protected intellectual property block, wherein limiting the operation of the portion of the protected intellectual property block comprises resetting a register in the programmable logic device to disable the portion.
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Accused Products
Abstract
Various techniques permit more thorough development of digital systems and devices by designers while protecting the proprietary interests of the owners of the intellectual property incorporated in such systems and devices. More specifically, the present invention provides to an end customer IP hardware which is suitable for prototype testing, but unusable for production purposes. One method limits the physical or electrical mode of operation of a hardware platform used for prototype testing of intellectual property (such as limiting the number of electrical contacts between the hardware and an external electrical device or limiting the data format(s) usable in the hardware during prototype testing). Another method limits the temporal operation of a hardware platform using an internal counter within the software provided by the intellectual property owner. Once a clock count limit is reached, the software disables the hardware in one or more prescribed ways, such as a reset of one or more registers, a global tri-state of the hardware 10, or a random failure of some type. Suitable hardware fabrication and/or augmentation also may be used to differentiate between the prototype and production manners of operation.
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Citations
12 Claims
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1. A method for limiting operation of a protected intellectual property block on a programmable logic device (PLD), the method comprising:
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(a) identifying license information associated with the protected intellectual property block, wherein the license information indicates whether the protected intellectual property block should be implemented with a limit on run time during which the protected intellectual property block can operate on the programmable logic device; (b) implementing the protected intellectual property block on the programmable logic device; and (c) limiting the operation of the protected intellectual property block on the programmable logic device based on the license information by limiting operation of a portion of the protected intellectual property block, wherein limiting the operation of the portion of the protected intellectual property block comprises resetting a register in the programmable logic device to disable the portion. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for disabling a programmable logic device (PLD) during operation of the programmable logic device, the method comprising:
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determining whether a run time limit has been set for a protected intellectual property block by using license information associated with the protected intellectual property block when implemented on the programmable logic device; measuring a time elapsed value during operation of the programmable logic device; and disabling the programmable logic device when the time elapsed value reaches the run time limit by imposing modal and operational limits on a portion of the protected intellectual property block and resetting a global tri-state of programmable logic device I/O. - View Dependent Claims (9, 10, 11)
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12. A programmable logic device (PLD) that is operationally limited during operation, comprising:
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a protected intellectual property block; a clock configured to measure a run time; a memory including a run time limit that has been selected at least in part using license information associated with the protected intellectual property block; and circuitry configured to disable the programmable logic device when the run time has reached the run time limit by resetting a register in the programmable logic device to disable operation of a portion of the protected intellectual property block.
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Specification