Across-thread out-of-order instruction dispatch in a multithreaded microprocessor
First Claim
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1. A method for executing a plurality of threads in a multithreaded processor, the method comprising:
- defining a plurality of threads, wherein each thread executes a sequence of program instructions and at least a subset of the plurality of threads are of different types;
fetching a first instruction for a first one of the plurality of threads;
fetching a second instruction for a second one of the plurality of threads, the second thread of a first type comprising a vertex thread type;
issuing the first instruction, wherein the first instruction has a latency period associated therewith; and
during the latency period associated with the first instruction, issuing the second instruction based at least in part on a priority ranking associated with the first type,wherein the first instruction and the second instruction are issued in an order independent of an order of fetching the first and second instructions, and wherein the second instruction is issued before one or more other instructions ready to issue for a longer duration than the second instruction, the one or more other instructions for a thread of a second type comprising a pixel thread type, wherein the pixel thread type is associated with a lower priority ranking than the priority ranking associated with the vertex thread type.
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Abstract
Instruction dispatch in a multithreaded microprocessor such as a graphics processor is not constrained by an order among the threads. Instructions for each thread are fetched, and a dispatch circuit determines which instructions in the buffer are ready to execute. The dispatch circuit may issue any ready instruction for execution, and an instruction from one thread may be issued prior to an instruction from another thread regardless of which instruction was fetched first. If multiple functional units are available, multiple instructions can be dispatched in parallel.
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Citations
19 Claims
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1. A method for executing a plurality of threads in a multithreaded processor, the method comprising:
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defining a plurality of threads, wherein each thread executes a sequence of program instructions and at least a subset of the plurality of threads are of different types; fetching a first instruction for a first one of the plurality of threads; fetching a second instruction for a second one of the plurality of threads, the second thread of a first type comprising a vertex thread type; issuing the first instruction, wherein the first instruction has a latency period associated therewith; and during the latency period associated with the first instruction, issuing the second instruction based at least in part on a priority ranking associated with the first type, wherein the first instruction and the second instruction are issued in an order independent of an order of fetching the first and second instructions, and wherein the second instruction is issued before one or more other instructions ready to issue for a longer duration than the second instruction, the one or more other instructions for a thread of a second type comprising a pixel thread type, wherein the pixel thread type is associated with a lower priority ranking than the priority ranking associated with the vertex thread type. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for executing a plurality of threads in a multithreaded processor, the method comprising:
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defining a plurality of threads, wherein each thread executes a sequence of program instructions and at least a subset of the plurality of threads are of different types; fetching a plurality of instructions, including; a first instruction for a first one of the plurality of threads, the first thread of a first type; a second instruction for a second one of the plurality of threads, the second thread of the first type comprising a vertex thread type; and a third instruction for a third one of the plurality of threads, the third thread of a second type comprising a pixel thread type, wherein the first instruction is fetched subsequently to the third instruction; issuing the first instruction to a first functional unit in the multithreaded processor prior to issuing the third instruction, based at least in part on a priority ranking associated with the first type; and in parallel with issuing the first instruction, issuing the second instruction to a second functional unit in the multithreaded processor, wherein the third instruction was ready to issue for a longer duration than the first instruction when the first instruction issued, and the pixel thread type is associated with a lower priority ranking than the priority ranking associated with the vertex thread type. - View Dependent Claims (12, 13, 14)
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15. A microprocessor configured for parallel processing of a plurality of threads, wherein each thread executes a sequence of program instructions, the microprocessor comprising:
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an execution module adapted to execute instructions for all of the plurality of threads, wherein at least a subset of the plurality of threads are of different types; a fetch circuit adapted to fetch instructions from a sequence of program instructions for each of the plurality of threads; and an issue circuit adapted to issue the instructions fetched by the fetch circuit to the execution module, wherein the instructions for different ones of the plurality of threads are issued in an order based at least in part on priority rankings based on respective thread types of the different threads and independent of an order in which the instructions for the different ones of the plurality of threads were fetched, wherein a pixel thread type is associated with a lower priority ranking than a priority ranking associated with a vertex thread type, the issue circuit being further adapted such that, during a latency period associated with a first issued instruction for a first one of the threads comprising a pixel thread, the issue circuit issues at least one instruction for a second one of the threads comprising a vertex thread. - View Dependent Claims (16, 17, 18, 19)
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Specification