Apparatus and method for coupling a plurality of test access ports to external test and debug facility

• US 7,676,698 B2
• Filed: 04/26/2006
• Issued: 03/09/2010
• Est. Priority Date: 04/27/2005
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: McGowan, Robert A.
• Primary Examiner(s): LE, DIEU MINH T
• Application Number:
  US11/411,670
• Publication Number:
  US 20060277436A1
• Time in Patent Office: 1,413 Days
• Field of Search: 714 30- 34, 714/27, 714/724, 714/733, 714/734
• US Class Current: 714/30
• CPC Class Codes: G06F 11/2236 to test CPU or processors

Abstract

An interface unit is provided for selectively testing a plurality of processor/cores. The interface unit includes an interface test access port (TAP) unit operable to receive test commands, and a logic unit coupled to the interface TAP unit and operable to generate control signals based on the received test commands to selectively generate a configuration of TAP units comprised in the plurality of processor/cores to receive test signals.

Claims

1. An interface unit for selectively testing a plurality of processor/cores, the interface unit comprising:

an interface test access port (TAP) unit operable to receive test commands; and

a logic unit coupled to the interface TAP for allowing the selection of multiple TAPs into one scan path and operable to generate control signals based on the received test commands to selectively generate a configuration of TAP units comprised in the plurality of processor/cores to receive test signals.

2. The interface unit as recited in claim 1 wherein the control signals generate a configuration of at least two TAP units for receiving a test data in (TDI) signal and returning a test data out (TDO) signal.

3. The interface unit as recited in claim 1 wherein the control signals generate a configuration of at least one TAP unit for receiving a TDI signal and returning a TDO signal.

4. The interface unit as recited in claim 3 wherein the control signals generate a configuration of at least two TAP units wherein a test clock (TCLK) signal is applied to a processor/core comprising one of the at least two TAP units and the TCLK signal is not applied to a processor/core comprising another one of the at least two TAP units.

5. The interface unit as recited in claim 1 further comprising a plurality of status and control registers coupled to the interface TAP unit, wherein the status registers are operable to store status information with respect to the processor/cores.

6. The interface unit as recited in claim 5 wherein the status information includes at least one selected from a group consisting of clock information, power information, and security information.

7. The interface unit as recited in claim 1 wherein the interface unit is responsive to signals from a security state machine.

8. The interface unit as recited in claim 1 wherein the control signals are applied to switch units coupled to the TAP units comprised in the plurality of processor/cores to selectively generate the configuration, the switch units configurable to control which test signals are received by the respective TAP units.

9. A method for selectively testing a plurality of processor/cores, each processor/core comprising a TAP unit, the method comprising:

receiving a test command designating selected processor/cores of the plurality of processor/cores in an interface TAP unit comprised in an interface unit, the interface unit coupled to the TAP units of the processor/cores for allowing the selection of multiple TAPs into one scan path;

generating control signals by the interface unit responsive to the test command; and

applying the control signals to generate a configuration of the TAP units of the selected processor/cores to receive test signals.

10. The method as recited in claim 9 wherein applying the control signals generates a configuration of at least two TAP units for receiving a TDI signal and returning a TDO signal.

11. The method as recited in claim 9 further comprising:

storing status information in the interface unit.

12. The method as recited in claim 9 wherein applying the control signals further comprises applying the control signals to a plurality of switch units to generate the configuration, each TAP unit having a switch unit coupled thereto, the switch unit configurable to control which test signals are received by the TAP unit.

13. The method as recited in claim 9 wherein applying the control signals generates a configuration of the TAP units of the selected processor/cores wherein a TCLK signal is received at some of the TAP units and the TCLK signal is not received at least one of the TAP units.

14. A system for selectively testing a plurality of processor/cores, the system comprising:

a plurality of processor/cores, each processor/core comprising a TAP unit; and

an interface unit coupled to the TAP units for allowing the selection of multiple TAPs into one scan path, the interface unit comprising an interface TAP unit operable to receive test commands and a logic unit operable to generate control signals based on the received test commands to selectively generate a configuration of the TAP units to receive test signals.

15. The system as recited in claim 14 wherein the interface unit further comprises a plurality of status registers, values in the status registers reflecting status of the processor/cores.

16. The system as recited in claim 15 wherein the values in the status registers designate at least one parameter selected from a group consisting of clock parameters, power parameters, and security parameters.

17. The system as recited in claim 14 wherein the control signals generate a configuration of selected TAP units for receiving a TDI signal and returning a TDO signal.

18. The system as recited in claim 14 wherein the control signals generate a configuration of selected TAP units wherein TCLK signals are received by some of the selected TAP units and TCLK signals are not received by at least one of the selected TAP units.

19. The system as recited in claim 14 further comprising a plurality of switch units coupled to the logic unit, each TAP unit having a switch unit coupled thereto, wherein the control signals are applied to the switch units to selectively generate the configuration of TAP units, the switch units configurable to control which test signals are received by the respective TAP units.

20. The system as recited in claim 15 further comprising a security state machine coupled to the logic unit, the security state machine storing the security status of the processor/cores, the security status of each processor/core in the state machine being stored in the status registers.