Process for the fabrication of an inertial sensor with failure threshold

• US 7,678,599 B2
• Filed: 12/04/2006
• Issued: 03/16/2010
• Est. Priority Date: 08/30/2002
• Status: Active Grant

• Current Assignee: Nokia Corporation, STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: Nokia Corporation, STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Zerbini, Sarah, De Masi, Biagio, Spinola Durante, Guido, Merassi, Angelo
• Primary Examiner(s): MENZ, LAURA MARY
• Application Number:
  US11/566,590
• Publication Number:
  US 20070175865A1
• Time in Patent Office: 1,198 Days
• Field of Search: 438/48, 438/52, 438/17
• US Class Current: 438/48
• CPC Class Codes: G01P 1/023 for acceleration measuring devices
• CPC Class Codes: G01P 15/06 using members subjected to a permanent deformation
• CPC Class Codes: G01P 15/0802 Details
• CPC Class Codes: G01P 15/0891 with indication of predetermined acceleration values G01P15/135 takes precedence
• CPC Class Codes: G01P 15/18 in two or more dimensions
• CPC Class Codes: G01P 2015/0814 for translational movement of the mass, e.g. shuttle type
• CPC Class Codes: H01H 1/0036 Switches making use of microelectromechanical systems [MEMS] for electromagnetic relays H01H50/005; for electrostatic relays H01H59/0009
• CPC Class Codes: H01H 35/146 operated by plastic deformation or rupture of structurally associated elements

Abstract

A process for the fabrication of an inertial sensor with failure threshold includes the step of forming, on top of a substrate of a semiconductor wafer, a sample element embedded in a sacrificial region, the sample element configured to break under a preselected strain. The process further includes forming, on top of the sacrificial region, a body connected to the sample element and etching the sacrificial region so as to free the body and the sample element. The process may also include forming, on the substrate, additional sample elements connected to the body.

Claims

1. A process for the fabrication of an inertial sensor with failure threshold, comprising the steps of:

forming, on top of a substrate of a semiconductor wafer, at least one sample element embedded in a sacrificial region;

forming, on top of said sacrificial region, a body connected to said sample element; and

etching said sacrificial region, so as to free said body and said sample element, said sample element being physically breakable, following etching of said sacrificial region, when subjected to a preselected strain.

2. The process according to claim 1, in which the step of forming said sample element comprises:

forming a first layer of a first material, which coats said substrate;

forming a second layer of a second material, which coats said first layer;

shaping said second layer, so as to define said sample element; and

forming a third layer of said first material coating said first layer and said sample element.

3. The process according to claim 2, in which said first material is a dielectric material and said second material is a conductive material.

4. The process according to claim 3, in which said first material is silicon dioxide and said second material is polysilicon.

5. The process according to claim 1 wherein the step of forming at least one sample element comprises the step of making at least one weakened region of said sample element.

6. The process according to claim 5, in which the step of making at least one weakened region comprises the step of defining a narrowing of said sample element.

7. The process according to claim 6 in which said step of defining a narrowing portion comprises forming notches in edges of said sample element.

8. The process according to claim 5 in which the step of making at least one weakened region comprises making a groove in a surface of said sample element and extending between opposite edges of said sample element.

9. The process according to claim 8, in which the step of making a groove comprises performing an etch of controlled duration of said sample element.

10. The process according to claim 8 in which the step of making a groove comprises:

forming a stop layer inside said sample element; and

etching said sample element until said stop element is reached.

11. The process according to claim 1 wherein the step of forming at least one sample element comprises defining at least one anchoring pad of said sample element.

12. The process according to claim 11, in which the step of etching said sacrificial region is interrupted before removing residual portions of said sacrificial region underlying said anchoring pad.

13. The process according to claim 1, further comprising making, before performing the step of forming said body, at least one first opening through said sacrificial region, which exposes one end of said sample element, and making second openings, which expose respective portions of said substrate.

14. The process according to claim 13, in which the step of forming said body comprises:

growing an epitaxial layer, which extends on top of said sacrificial region and through said first opening and said second openings; and

etching said epitaxial layer until said sacrificial region is reached.

15. The process according to claim 14, in which, during the step of etching said epitaxial layer there are defined anchorages connected to said substrate and elastic elements connecting said body to said anchorages.

21. The process of claim 1, comprising forming, in said sacrificial region, a via over said sample element, and wherein said step of forming the body comprises connecting the body to said sample element through said via.

22. The process of claim 1 wherein said step of forming said sample element comprises forming a plurality of sample elements, of which said sample element is one, each of the plurality of sample elements being coupled at a respective first end to the semiconductor substrate and at a respective second end to said semiconductor material body.

23. The process of claim 1, further comprising forming, in said semiconductor wafer, a test circuit configured to detect a break in said sample element.

16. A method for manufacturing an inertial sensor, comprising:

forming, on a semiconductor substrate, a sample element having a first end coupled to the substrate, and

forming the sample element being configured to physically break under a preselected strain; and

forming, above the semiconductor substrate, a semiconductor material body coupled to a second end of the sample element.

17. The method of claim 16 wherein the forming the sample element comprises forming the sample element in a T shape, the first end forming a cross-bar portion of the T and being coupled to the substrate at extreme ends of the crossbar, the second end extending from a central portion of the crossbar to form the T.

18. The method of claim 16, further comprising forming an additional sample element having a first end coupled to the substrate, a second end coupled to the semiconductor material body, and configured to break under the preselected strain.

19. The method of claim 16, further comprising forming a weakened region on the sample element, and wherein the sample element is configured to break at the weakened region under the preselected strain.

20. The method of claim 19 wherein the weakened region comprises a narrowed region of the sample element.

24. The method of claim 16, further comprising forming a circuit on the semiconductor substrate, configured to subject the sample element to a voltage such as to cause an electric current to flow through the sample element.

25. The method of claim 24 wherein the circuit is further configured to detect the current flowing in the sample element.

30. The method of claim 16, comprising forming the semiconductor material body with a mass sufficient that, if the inertial sensor is subjected to a predetermined acceleration, the mobile mass will subject the sample element to the preselected strain, causing the sample element to break.

31. The method of claim 16 wherein the forming the sample element comprises forming the sample element in an L shape, and forming the sample element to break at a vertex of the L when the sample element is subjected to the preselected strain.

32. The method of claim 16 wherein the forming the sample element comprises forming the sample element in a rectilinear shape.

33. The method of claim 16, comprising forming a plurality of spring elements, each coupled at a respective first end to the semiconductor substrate and at a respective second end to the semiconductor material body, and forming each of the spring elements to have a mechanical resistance to failure that is greater than that of the sample element.

26. A process for the fabrication of an inertial sensor with failure threshold, comprising:

forming, on top of a substrate of a semiconductor wafer, a conductive sample element coupled at a first end thereof to the substrate and shaped so as to be subject to a stress when a second end thereof is outside a relative resting position with respect to the substrate, and wherein configuring the conductive sample element is configured so as to undergo a physical failure in a controlled way when subjected to a stress of pre-selected intensity; and

forming a body connected to the second end of the sample element.

27. The process of claim 26, further comprising forming, in the semiconductor wafer, a test circuit configured to detect a change in electrical resistance of the sample element.

28. The process of claim 26 wherein the step of forming a conductive sample element comprises forming a plurality of sample elements of which the sample element is one, each of the sample element being coupled at respective first ends to the substrate and at respective second ends to the body, and each of the sample elements being configured to undergo failure in a controlled way when subjected to the stress of pre-selected intensity.

29. The process of claim 26 wherein the step of forming a sample element comprises the step of making a weakened region of said sample element.