Process for manufacturing a membrane of semiconductor material integrated in, and electrically insulated from, a substrate

• US 7,678,600 B2
• Filed: 03/13/2008
• Issued: 03/16/2010
• Est. Priority Date: 03/14/2007
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Corona, Pietro, Combi, Chantal, Barlocchi, Gabriele, Villa, Flavio Francesco, Baldo, Lorenzo
• Primary Examiner(s): Coleman; W. David
• Assistant Examiner(s): WHITE, SHAKA SHAKAR
• Application Number:
  US12/047,830
• Publication Number:
  US 20080224242A1
• Time in Patent Office: 733 Days
• Field of Search: None
• US Class Current: 438/48
• CPC Class Codes: B81C 1/00158 Diaphragms, membranes manufacture process for semi-permeable inorganic membranes B01D67/0039
• CPC Class Codes: B81C 2201/0116 Thermal treatment for structural rearrangement of substrate atoms, e.g. for making buried cavities

Abstract

A process for manufacturing an integrated membrane made of semiconductor material includes the step of forming, in a monolithic body of semiconductor material having a front face, a buried cavity, extending at a distance from the front face and delimiting with the front face a surface region of the monolithic body, the surface region forming a membrane that is suspended above the buried cavity. The process further envisages the step of forming an insulation structure in a surface portion of the monolithic body to electrically insulate the membrane from the monolithic body; and the further and distinct step of setting the insulation structure at a distance from the membrane so that it will be positioned outside the membrane at a non-zero distance of separation.

Claims

1. A process for manufacturing an insulated membrane made of semiconductor material, comprising:

forming, in a monolithic body of semiconductor material having a front face, a buried cavity extending at a distance from said front face and delimiting with said front face a surface region of said monolithic body, said surface region forming a membrane that is suspended above said buried cavity;

forming an insulation structure in a surface portion of said monolithic body such as to electrically insulate said membrane from said monolithic body; and

setting said insulation structure at a distance from said membrane so that said insulation structure is positioned outside, and at a non-zero distance of separation from said membrane.

2. The process according to claim 1, wherein said membrane is continuous and formed by a single portion of semiconductor material, and said buried cavity is contained and completely insulated within said monolithic body.

3. The process according to claim 1, wherein said distance of separation, measured in a plane parallel to said front face, is comprised between 1 and 100 μ

m, preferably between 1 and 50 μ

m.

4. The process according to claim 1, wherein said step of setting at a distance comprises forming in said monolithic body a connecting structure, made of insulating material, adjacent to, and surrounding entirely, said buried cavity, subsequent to said step of forming said buried cavity;

and said step of forming an insulation structure comprises forming said insulation structure outside, and surrounding, said membrane, and extending vertically starting from said front face as far as said connecting structure, joining therewith.

5. The process according to claim 4, wherein said step of forming said connecting structure is carried out substantially while said step of forming said insulation structure is carried out.

6. The process according to claim 4, wherein said connecting structure extends up to scribing lines of said monolithic body.

7. The process according to claim 4, wherein said step of forming a buried cavity comprises:

forming first buried channels within a first region of said monolithic body, said buried channels delimiting first separation structures made of semiconductor material; and

carrying out a thermal treatment such as to cause migration of the semiconductor material of said first separation structures towards said front face, the elimination of said first separation structures, and the transformation of said first buried channels into said buried cavity;

and wherein said step of forming a connecting structure comprises;

forming second buried channels within a second region of said monolithic body adjacent to, and surrounding, said first region, delimiting second separation structures made of semiconductor material, said second separation structures having greater dimensions, and/or being set at a greater distance apart, with respect to said first separation structures, said thermal treatment consequently causing thinning-out of said second separation structures; and

oxidizing completely said second separation structures.

8. The process according to claim 7, wherein said step of oxidizing completely further comprises oxidizing internal walls of said buried cavity and of said second buried channels.

9. The process according to claim 7, wherein said steps of forming first and second buried channels comprise:

digging first and second deep trenches within said first and second regions, respectively, of said monolithic body, delimiting said first and second separation structures, respectively; and

performing an epitaxial growth so as to close at the top said first and second deep trenches with a closing layer made of semiconductor material,

and wherein said step of forming said insulation structure comprises;

digging a vertical trench through said closing layer, such as to reach said second buried channels; and

introducing oxygen through said vertical trench so as to form an insulating coating on internal walls of said vertical trench, said step of introducing oxygen also causing said step of oxidizing completely said second separation structures.

10. The process according to claim 9, wherein forming said insulation structure further comprises, after said step of oxidizing, forming within said vertical trench an insulating filling region so as to fill said trench completely.

11. The process according to claim 1, wherein said step of forming said insulation structure comprises forming said insulation structure inside said membrane, at an external portion and along an entire perimeter thereof, extending from said front face as far as said buried cavity;

and wherein said step of setting at a distance comprises introducing, through said insulation structure, within a peripheral portion of said buried cavity, a filling material, so as to fill said peripheral portion and confine said membrane above a portion of said buried cavity inside said peripheral portion.

12. The process according to claim 11, wherein said filling material is polysilicon.

13. The process according to claim 11, wherein said step of forming an insulation structure comprises:

forming in said external portion of said membrane a plurality of access trenches, separated from one another by connection elements made of semiconductor material connecting said membrane to a substrate of said monolithic body; and

oxidizing completely said connection elements and internal walls of said access trenches,

wherein said step of setting at a distance comprising introducing said filling material through said access trenches.

14. The process according to claim 13, wherein said access trenches are aligned along external sides of said membrane and extend parallel to, and set in one or two rows alongside one another, or else in a direction transverse to, said external sides.

15. The process according to claim 1, further comprising:

forming a buried connection channel laterally with respect to, and in fluid connection with, said buried cavity; and

forming a duct for access to said buried connection channel starting from an external face of said monolithic body, said insulation structure also surrounding said buried connection channel.

16. A microelectromechanical structure, comprising:

a monolithic body of semiconductor material having a front face; and

a buried cavity, extending at a distance from said front face and delimiting with said front face a membrane, which is suspended above said buried cavity; and

an insulation structure in a surface portion of said monolithic body, surrounding said membrane at a non-zero distance of separation and configured to electrically insulate said membrane from said monolithic body.

17. The microelectromechanical structure according to claim 16, wherein said membrane is continuous and formed by a single portion of semiconductor material, and said buried cavity is completely contained within said monolithic body.

18. The microelectromechanical structure according to claim 16, wherein said distance of separation, measured in a plane parallel to said front face, is in the range of 1 and 100 μ

m, preferably in the range of 1 and 50 μ

m.

19. The microelectromechanical structure according to claim 16, further comprising a connecting structure, made of insulating material, adjacent to, and surrounding entirely, said buried cavity;

said insulation structure extending vertically starting from said front face as far as said connecting structure, joining therewith.

20. The microelectromechanical structure according to claim 19, wherein said insulation structure comprises a coating of insulating material and, within said coating, a filling material;

said filling material delimiting said buried cavity.

21. The microelectromechanical structure according to claim 20, wherein said filling material is polysilicon.

22. The microelectromechanical structure according to claim 16, further comprising:

a buried connection channel set laterally with respect to, and in fluid connection with, said buried cavity; and

an access duct for access to said buried connection channel, extending from said front face of said monolithic body;

said insulation structure also surrounding said buried connection channel.

23. A sensor device comprising a microelectromechanical structure according to claim 16.

24. The device according to claim 23, comprising one from among:

an absolute or differential pressure sensor, an inertial sensor, a chemical sensor, a magnetic-field sensor, and a microphone.

25. A process, comprising:

forming at least two voids in a substrate and a membrane formed from the substrate material to completely cover at least one of the at least two voids;

forming a trench completely around the membrane at a non-zero distance from the membrane and extending into the substrate to a depth that is at least a depth of at least one of the at least two voids in the substrate and in communication with at least one of the at least two voids; and

forming a buried insulation region completely around the trench and all of the at least two voids via the trench to electrically insulate the membrane from a remainder of the substrate.

26. The process of claim 25, further comprising filling the trench and all but one of the at least two voids with a dielectric material to form a single uniform electrical and thermal insulation structure around the membrane while leaving a remaining void below the membrane to provide functionality to the membrane.

27. The process of claim 26, wherein forming at least two voids and a membrane comprises forming at least one buried cavity and at least one buried channel and filling all but one of the at least one buried cavity and all of the buried channels with the dielectric material via the trench.

28. The process of claim 27, wherein the trench is filled with the dielectric material.

29. The process of claim 25, wherein forming the membrane and the at least two voids comprises etching the substrate to form a plurality of columns and performing epitaxial growth on the columns to merge a top portion of the columns to form the membrane of monocrystalline silicon that is flexible and adapted to flex above one of the at least two voids in the presence of external stress.

30. The process of claim 25, wherein the trench is formed away from the membrane and anchorages of the membrane to the substrate a distance of separation to prevent mechanical stresses on the membrane due to discontinuity represented by a silicon-oxide junction created by the insulation structure.