Circuit board manufacturing method and circuit board

• US 7,679,004 B2
• Filed: 03/02/2005
• Issued: 03/16/2010
• Est. Priority Date: 03/03/2004
• Status: Expired due to Fees

• Current Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited), Mitsubishi Paper Mills Limited
• Original Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited), Mitsubishi Paper Mills Limited
• Inventors: Natsuka, Masanori, Aizawa, Wakana, Komuro, Toyokazu, Sakai, Toyoaki, Kaneda, Yasuo, Fukase, Katsuya, Irisawa, Munetoshi
• Primary Examiner(s): Norris; Jeremy C
• Application Number:
  US10/598,524
• Publication Number:
  US 20070181994A1
• Time in Patent Office: 1,840 Days
• Field of Search: 174262-266, 361/774, 361792-795
• US Class Current: 174/262
• CPC Class Codes: H05K 1/116 Lands, clearance holes or other lay-out details concerning the surrounding of a via
• CPC Class Codes: H05K 2201/09381 Shape of non-curved single flat metallic pad, land or exposed part thereof; Shape of electrode of leadless component
• CPC Class Codes: H05K 2201/09563 Metal filled via
• CPC Class Codes: H05K 2201/09581 Applying an insulating coating on the walls of holes
• CPC Class Codes: H05K 2201/098 Special shape of the cross-section of conductors, e.g. very thick plated conductors
• CPC Class Codes: H05K 2203/0517 Electrographic patterning
• CPC Class Codes: H05K 2203/0577 Double layer of resist having the same pattern
• CPC Class Codes: H05K 2203/0582 Coating by resist, i.e. resist used as mask for application of insulating coating or of second resist
• CPC Class Codes: H05K 2203/1184 Underetching, e.g. etching of substrate under conductors or etching of conductor under dielectrics; Means for allowing or controlling underetching
• CPC Class Codes: H05K 2203/1394 Covering open PTHs, e.g. by dry film resist or by metal disc
• CPC Class Codes: H05K 3/0094 Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
• CPC Class Codes: H05K 3/061 Etching masks
• CPC Class Codes: H05K 3/064 Photoresists
• CPC Class Codes: H05K 3/065 applied by electrographic, electrophotographic or magnetographic methods
• CPC Class Codes: H05K 3/108 by semi-additive methods; masks therefor characterised by metallic etch mask H05K3/062; electroplating methods or apparatus H05K3/241
• CPC Class Codes: H05K 3/421 Blind plated via connections H05K3/422, H05K3/423 and H05K3/425 take precedence
• CPC Class Codes: H05K 3/427 initial plating of through-holes in metal-clad substrates

Abstract

As means for solving a problem of a positional shift of a land and a hole which is caused by an alignment in the formation of an etching resist layer and a plated resist layer in a method of manufacturing a circuit board, there are provided a method of manufacturing a circuit board including the steps of forming a first resin layer on a surface of an insulating substrate having a conductive layer on the surface and an internal wall of a through hole or/and a non-through hole, forming a second resin layer which is insoluble or slightly soluble in a developing solution for the first resin layer on the first resin layer provided on the surface conductive layer, and removing the first resin layer provided over the hole with the developing solution for the first resin layer, and a method of manufacturing a circuit board including the step of uniformly charging a surface of the first resin layer to induce a potential difference to the first resin layer provided over the hole and the first resin layer provided on the surface conductive layer before forming the second resin layer. Moreover, there is provided a circuit board having a hole with a small positional shift and high precision.

Claims

1. A circuit board in which a circuit portion is formed on an insulating substrate by a conductive layer and there provided a through hole and/or a non-through hole having an internal wall covered or filled with the conductive layer, wherein a land of the through hole and/or the non-through hole is formed continuously like a concentric circle with respect to the hole, a maximum height of the conductive layer in a non-coupling portion of the land is equal to or greater than −

5 μ

m with a corner portion of the insulating substrate set to be a reference point and is equal to or smaller than a thickness of the conductive layer in a circuit portion, and a land width from the reference point is 0 to 40 μ

m,

wherein the land width falls between a maximum value and a minimum value, and wherein a difference between the maximum and minimum values is equal to or less than 8 μ

m and greater than 0 μ

m.

2. The circuit board according to claim 1, wherein a sectional shape of the conductive layer in the circuit portion is different from that of the conductive layer in the land portion.

3. The circuit board according to claim 2, wherein a portion having a maximum height is present within a range from the internal wall of the hole to a thickness of the conductive layer in the hole in the conductive layer of the land.