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Vertical-type non-volatile memory devices

  • US 7,679,133 B2
  • Filed: 11/03/2008
  • Issued: 03/16/2010
  • Est. Priority Date: 11/08/2007
  • Status: Active Grant
First Claim
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1. A semiconductor device comprising:

  • a substrate extending in a horizontal direction;

    a plurality of interlayer dielectric layers on the substrate;

    a plurality of gate patterns, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer;

    a vertical channel extending in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns;

    a gate insulating layer between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel; and

    a charge trapping layer between each corresponding gate pattern and gate insulating layer, the charge trapping layer including;

    a first portion extending in the vertical direction between the gate pattern and the gate insulating layer;

    a second portion extending in the horizontal direction between the gate pattern and the neighboring upper interlayer dielectric layer; and

    a third portion extending in the horizontal direction between the gate pattern and the neighboring lower interlayer dielectric layer.

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