Localized temperature control during rapid thermal anneal

• US 7,679,166 B2
• Filed: 02/26/2007
• Issued: 03/16/2010
• Est. Priority Date: 02/26/2007
• Status: Expired due to Fees

• Current Assignee: Ultratech Incorporated (Veeco Instruments Incorporated)
• Original Assignee: International Business Machines Corporation
• Inventors: Nowak, Edward J., Anderson, Brent A.
• Primary Examiner(s): Tran; Minh-Loan T
• Assistant Examiner(s): KUO, WENSING W
• Application Number:
  US11/678,783
• Publication Number:
  US 20080203523A1
• Time in Patent Office: 1,114 Days
• Field of Search: 257/506, 257/510, 257/513, 257/629, 257/638, 257/640, 257/647, 257/649, 257/E21.54, 257/E21.545, 257/E21.546, 257/E29.026
• US Class Current: 257/638
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

Disclosed herein are embodiments of a semiconductor structure and an associated method of forming the semiconductor structure with shallow trench isolation structures having selectively adjusted reflectance and absorption characteristics in order to ensure uniform temperature changes across a wafer during a rapid thermal anneal and, thereby, limit variations in device performance. Also disclosed are embodiments of another semiconductor structure and an associated method of forming the semiconductor structure with devices having selectively adjusted reflectance and absorption characteristics in order to either selectively vary the performance of individual devices (e.g., to form devices with different threshold voltages (Vt) on the same wafer) and/or to selectively optimize the anneal temperature of individual devices (e.g., to ensure optimal activation temperatures for n-type and p-type dopants during anneals).

Claims

1. A semiconductor structure comprising:

a substrate;

a device above said substrate, wherein said device comprises a first material with a first reflectivity; and

a trench isolation region above said substrate and positioned laterally adjacent to said device, wherein said trench isolation region comprises;

a trench having sidewalls;

a second material with a second reflectivity in said trench; and

a third material with a third reflectivity in contact with said second material,

wherein said third material does not extend laterally beyond said sidewalls, and

wherein a location of said third material relative to said second material and a ratio of an amount of said third material to an amount of said second material are predetermined such that said third material balances differences between said first reflectivity of said first material of said device and said second reflectivity of said second material of said trench isolation region in order to make reflectance and absorption characteristics of said device and said trench isolation region approximately uniform.

2. The semiconductor structure of claim 1, wherein said third material is completely embedded within said second material such that said second material surrounds said third material on all sides.

3. The semiconductor structure of claim 1, wherein said third material is above said second material and not said first material.

4. The semiconductor structure of claim 1, wherein said third material is partially embedded within said second material such that a first portion of said third material is positioned within an upper one-half only of said trench and a second portion of said third material is above said second material.

5. The semiconductor structure of claim 1, wherein said substrate comprises one of a bulk semiconductor substrate and an insulator layer on a semiconductor substrate.

6. The semiconductor structure of claim 1, wherein said first material comprises a semiconductor, said second material comprises an insulator, and said third material comprises at least one of a second insulator and a spin-on dielectric material.

7. A semiconductor structure comprising:

a substrate;

a first device above said substrate;

a second device above said substrate adjacent to said first device; and

a dielectric material in a pattern on said first device and not on said second device,

wherein an amount of said first device covered by said pattern is predetermined so as to selectively adjust a first reflectivity of said first device relative to a second reflectivity of said second device.

8. The semiconductor structure of claim 7, wherein said dielectric material comprises one of an oxide and a nitride.

9. The semiconductor wafer structure of claim 7, where a thickness of said dielectric material is predetermined so that a reflectance difference is exhibited between areas of said first device with and without said dielectric material.

10. The semiconductor structure of claim 7, wherein said first device is bordered by isolation regions and wherein said pattern overlaps both said first device and said isolation regions.

11. The semiconductor structure of claim 7, wherein said second device is essentially identical to said first device and wherein said amount of said first device covered by said pattern is predetermined in order to selectively increase said first reflectivity of said first device relative to said second reflectivity of said second device and to, thereby, selectively increase a first threshold voltage of said first device relative to a second threshold voltage of said second device.

12. The semiconductor structure of claim 7, wherein said first device comprises a p-type field effect transistor and said second device comprises an n-type field effect transistor and wherein said amount of said first device covered by said pattern is predetermined such that a first maximum temperature achievable by said p-type field effect transistor is less than a second maximum temperature achievable by said n-type field effect transistor during a rapid thermal anneal process.

13. The semiconductor structure of claim 7, wherein said first device comprises a first semiconductor material and said second device comprises a second semiconductor material, wherein said first semiconductor material and said second semiconductor material have different reflectivities and wherein said amount of said first device covered by said pattern is predetermined so as to balance said different reflectivities in order to make reflectance and absorption characteristics of said first device and said second approximately uniform.

14. The semiconductor structure of claim 13, wherein said first semiconductor material comprises silicon germanium and said second semiconductor material comprises silicon.

15. A semiconductor structure comprising:

a substrate;

a first device above said substrate;

a second device above said substrate adjacent to said first device,

a dielectric material in a first pattern on said first device and in a second pattern different from said first pattern on said second device, wherein a first amount of said first device covered by said first pattern and a second amount of said second device covered by said second pattern are different and are predetermined so that reflectivities of said first device and said second device are selectively adjusted.

16. The semiconductor structure of claim 15, wherein said dielectric material comprises one of an oxide and or a nitride.

17. The semiconductor structure of claim 15, where a thickness of said dielectric material is predetermined so that reflectance differences are exhibited between areas of said first device and said second device with and without said dielectric material, respectively.

18. The semiconductor structure of claim 15, wherein said second device is essentially identical to said first device, wherein said first amount and said second amount are each independently predetermined in order to selectively and independently control threshold voltages of said first device and said second device, and wherein said first amount is greater than said second amount such that a first threshold voltage of said first device is greater than a second threshold voltage of said second device.

19. The semiconductor structure of claim 15, wherein said first device comprises a p-type field effect transistor and said second device comprises an n-type field effect transistor, wherein said first amount and said second amount are predetermined in order to selectively and independently control maximum temperatures achievable by said first device and said second device during a rapid thermal anneal process, wherein said first amount is greater than said second amount such that a first maximum temperature achievable by said p-type field effect transistor is less than a second maximum temperature achievable by said n-type field effect transistor during a rapid thermal anneal process.

20. The semiconductor structure of claim 15, wherein said first device and said second device are bordered by isolation regions and wherein said first pattern and said second pattern overlap said isolation regions.