Low-loss impedance-matched source-follower for repeating or switching signals on a high speed link

• US 7,679,395 B1
• Filed: 09/15/2008
• Issued: 03/16/2010
• Est. Priority Date: 09/15/2008
• Status: Active Grant

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Zhang, Shengyuan, Yang, Yunfu, Wang, Shoujun, Zhang, Yu Min
• Primary Examiner(s): Le; Don P
• Application Number:
  US12/210,316
• Publication Number:
  US 20100066410A1
• Time in Patent Office: 547 Days
• Field of Search: 326/26, 326/27, 326/30, 326 82- 87
• US Class Current: 326/27
• CPC Class Codes: H03K 19/00384 in field effect transistor circuits
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0278 Arrangements for impedance matching

Abstract

Switching and repeating applications using an impedance matched source follower improve performance of high speed links such as PCI Express, HDMI, DisplayPort and DVI by reducing attenuation and other degradation of high speed signals, including those with transmit pre-emphasis, by avoiding impedance discontinuities over process, voltage and temperature variations and by driving a broader range of loads, e.g., heavily capacitive loads. A circuit for switching or repeating signals on a single-ended or differential high speed link may comprise a source follower with input and output impedances matched to input and output transmission lines on the high speed link. The source follower is biased by a constant transconductance circuit, an external calibration circuit or other circuit to provide an essentially constant output impedance over process, voltage and temperature variations.

Claims

1. A circuit for switching or repeating signals on a high speed link comprising:

an input and an output for coupling, respectively, to input and output transmission lines for the high speed link;

a termination resistor coupling the input to a termination voltage;

a first transistor, having first gate, source and drain terminals, configured as a source follower wherein the first gate terminal is coupled to the input, the first source terminal is coupled to the output and the first drain terminal is coupled to a voltage source; and

a bias current circuit coupled to the first source terminal and output for providing bias current for the first transistor resulting in essentially constant output impedance over process, voltage and temperature variations.

2. The circuit of claim 1, wherein the bias current circuit comprises:

a constant transconductance bias circuit; and

a second transistor, having second gate, source and drain terminals, wherein the second drain terminal is coupled to the first source terminal and the output, the second source terminal is coupled to ground and the second gate terminal is coupled to the constant transconductance bias circuit.

3. The circuit of claim 1, wherein the bias current circuit comprises an external calibration circuit.

4. The circuit of claim 1, wherein the termination voltage is one-half or two-thirds of the voltage source.

5. The circuit of claim 1, wherein the termination resistor approximately matches an impedance of the input transmission line.

6. The circuit of claim 1, the first transistor further comprising a first bulk terminal, wherein the first bulk terminal is coupled to the first source terminal.

7. The circuit of claim 1, wherein the high speed link comprises one of Peripheral Component Interconnect (PCI) Express, High Definition Multimedia Interface (HDMI), DisplayPort and Digital Visual Interface (DVI).

8. The circuit of claim 1, wherein the high speed link implements transmit pre-emphasis to compensate for transmission losses or distortions.

9. A circuit for switching or repeating signals on a differential signal high speed link comprising:

a differential input comprising positive input and negative input for coupling to differential input transmission lines for the high speed link;

a differential output comprising positive output and negative output for coupling to differential output transmission lines for the high speed link;

a first termination resistor coupling the positive input to a termination voltage;

a second termination resistor coupling the negative input to the termination voltage;

a first transistor, having first gate, source and drain terminals, configured as a source follower wherein the first gate terminal is coupled to the positive input, the first source terminal is coupled to the positive output and the first drain terminal is coupled to a voltage source;

a second transistor, having second gate, source and drain terminals, configured as a source follower wherein the second gate terminal is coupled to the negative input, the second source terminal is coupled to the negative output and the second drain terminal is coupled to the voltage source; and

a bias current circuit coupled to the first and second source terminals and the positive and negative outputs for providing bias currents for the first and second transistors resulting in essentially constant output impedance over process, voltage and temperature variations.

10. The circuit of claim 9, wherein the bias current circuit comprises:

a constant transconductance bias circuit;

a third transistor, having third gate, source and drain terminals, wherein the third drain terminal is coupled to the first source terminal and the positive output, the third source terminal is coupled to ground and the third gate terminal is coupled to the constant transconductance bias circuit; and

a fourth transistor, having fourth gate, source and drain terminals, wherein the fourth drain terminal is coupled to the second source terminal and the negative output, the fourth source terminal is coupled to ground and the fourth gate terminal is coupled to the constant transconductance bias circuit.

11. The circuit of claim 9, wherein the bias current circuit comprises an external calibration circuit.

12. The circuit of claim 9, wherein the termination voltage is one-half or two-thirds of the voltage source.

13. The circuit of claim 9, wherein each of the first termination resistor approximately matches an impedance of the positive input transmission line and the second termination resistor approximately matches an impedance of the negative input transmission line.

14. The circuit of claim 9, the first transistor further comprising a first bulk terminal and the second transistor further comprising a second bulk transistor, wherein the first bulk terminal is coupled to the first source terminal and the second bulk terminal is coupled to the second source terminal.

15. The circuit of claim 9, wherein the high speed link comprises one of Peripheral Component Interconnect (PCI) Express, High Definition Multimedia Interface (HDMI), DisplayPort and Digital Visual Interface (DVI).

16. The circuit of claim 9, wherein the high speed link implements transmit pre-emphasis to compensate for transmission losses or distortions.

17. A system for switching or repeating signals on a high speed link comprising:

a high speed link comprising input and output transmission lines;

a transmitter coupled to the input transmission line;

a receiver coupled to the output transmission line; and

a circuit coupled between the input and output transmission lines for switching or repeating signals transmitted onto the input transmission line by the transmitter, the circuit comprising;

an input and an output for coupling, respectively, to the input and output transmission lines;

a termination resistor coupling the input to a termination voltage;

a first transistor, having first gate, source and drain terminals, configured as a source follower wherein the first gate terminal is coupled to the input, the first source terminal is coupled to the output and the first drain terminal is coupled to a voltage source; and

a bias current circuit coupled to the first source terminal and output for providing bias current for the first transistor resulting in essentially constant output impedance over process, voltage and temperature variations.

18. The circuit of claim 17, wherein the bias current circuit comprises:

a constant transconductance bias circuit; and

a second transistor, having second gate, source and drain terminals, wherein the second drain terminal is coupled to the first source terminal and the output, the second source terminal is coupled to ground and the second gate terminal is coupled to the constant transconductance bias circuit.

19. The circuit of claim 17, wherein the high speed link comprises a differential high speed link.

20. The circuit of claim 17, wherein the high speed link comprises one of Peripheral Component Interconnect (PCI) Express, High Definition Multimedia Interface (HDMI), DisplayPort and Digital Visual Interface (DVI).