Attenuator with bias control circuit
First Claim
1. An attenuator, comprising:
- an input port, an output port, an attenuation control port, and first and second supply voltages;
a first series attenuation branch, including a first field effect transistor, connected between the input port and an intermediate node;
a second series attenuation branch, including a second field effect transistor, connected between the node and the output port;
a shunt attenuation branch, including a third field effect transistor, connected between the intermediate node and the first supply voltage connection, a gate of third field effect transistor receiving the attenuation control signal from the attenuation control port; and
a bias control circuit, comprisinga fourth field effect transistor receiving at a gate thereof the attenuation control signal from the attenuation control port, and having a first terminal connected to the first supply voltage, anda resistor connected between a second terminal of the fourth field effect transistor and the second supply voltage,wherein a voltage at the second terminal of the fourth field effect transistor is coupled to gates of the first and second field effect transistors to supply a bias voltage thereto in response to the attenuation control signal.
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Accused Products
Abstract
An attenuator includes one or more series attenuation branches including one or more series field effect transistors (FETs) each having a gate; one or more shunt attenuation branches including one or more shunt FETs each having a gate; and a bias control FET. The bias control FET receives at its gate a first bias control signal and in response thereto produces at one of its drain and source terminals a second bias control signal. Either the first bias control signal is coupled to the gates of one or more series FETs, and the second bias control signal is coupled to the gates of the one or more shunt FETs; or the first bias control signal is coupled to the gates of the one or more shunt FETs, and the second bias control signal is coupled to the gates of the one or more series FETs.
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Citations
19 Claims
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1. An attenuator, comprising:
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an input port, an output port, an attenuation control port, and first and second supply voltages; a first series attenuation branch, including a first field effect transistor, connected between the input port and an intermediate node; a second series attenuation branch, including a second field effect transistor, connected between the node and the output port; a shunt attenuation branch, including a third field effect transistor, connected between the intermediate node and the first supply voltage connection, a gate of third field effect transistor receiving the attenuation control signal from the attenuation control port; and a bias control circuit, comprising a fourth field effect transistor receiving at a gate thereof the attenuation control signal from the attenuation control port, and having a first terminal connected to the first supply voltage, and a resistor connected between a second terminal of the fourth field effect transistor and the second supply voltage, wherein a voltage at the second terminal of the fourth field effect transistor is coupled to gates of the first and second field effect transistors to supply a bias voltage thereto in response to the attenuation control signal. - View Dependent Claims (2, 3, 4, 5)
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6. An attenuator comprising:
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one or more series attenuation branches comprising one or more series field effect transistors, each having a gate; one or more shunt attenuation branches comprising one or more shunt field effect transistors, each having a gate; and one selected from the group consisting of;
(1) a bias control field effect transistor which receives at its gate a first bias control signal and in response thereto produces at one of its drain and source terminals a second bias control signal, wherein the first bias control signal is coupled to the gates of the one or more series field effect transistors, and the second bias control signal is coupled to the gates of the one or more shunt field effect transistors; and
(2) a bias control field effect transistor which receives at its gate a first bias control signal and in response thereto produces at one of its drain and source terminals a second bias control signal, wherein the first bias control signal is coupled to the gates of the one or more shunt field effect transistors, and the second bias control signal is coupled to the gates of the one or more series field effect transistors. - View Dependent Claims (7, 8, 9, 10, 11, 12)
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13. A method of attenuating a signal, the method comprising:
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providing one or more series attenuation branches comprising one or more series field effect transistors, each having a gate; providing one or more shunt attenuation branches comprising one or more shunt field effect transistors, each having a gate; receiving a first bias control signal and providing the bias control signal to a bias control field effect transistor; at the bias control field effect transistor, producing from the first bias control signal a second bias control signal having a voltage which changes in an opposite direction with respect to a change in voltage of the first bias control signal; and one selected from the group consisting of;
(1) coupling the first bias control signal to the gates of each of the one or more series field effect transistors, and the second bias control signal is applied to the gates of the one or more shunt field effect transistors; and
(2) coupling the first bias control signal to the gates of the one or more shunt field effect transistors, and the second bias control signal is applied to the gates of the one or more series field effect transistors. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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Specification