System and method for common mode translation

• US 7,679,443 B2
• Filed: 03/29/2007
• Issued: 03/16/2010
• Est. Priority Date: 08/31/2006
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Fayed, Ayman A., Haroun, Baher, Byrd, Russell
• Primary Examiner(s): Nguyen; Linh V
• Application Number:
  US11/729,487
• Publication Number:
  US 20080238746A1
• Time in Patent Office: 1,083 Days
• Field of Search: 330/9, 330250-261
• US Class Current: 330/258
• CPC Class Codes: H03M 3/488 using automatic control

Abstract

System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network, computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.

Claims

1. A method for tuning a circuit, the method comprising:

determining a difference between a common mode level of an input signal to the circuit and a desired common mode level;

generating a compensation signal based on the difference; and

applying the compensation signal to current sinks coupling inputs of the circuit to an electrical ground.

2. The method of claim 1, wherein the determining comprises comparing the input signal with the desired common mode level.

3. The method of claim 2, wherein the input signal comprises a differential mode signal, and wherein the comparing comprises comparing a positive input signal and a negative input signal with the desired common mode level.

4. The method of claim 3, wherein the generating comprises generating a bias voltage.

5. The method of claim 4, wherein the applying comprises applying the bias voltage to the current sinks.

6. The method of claim 1, wherein the determining comprises specifying a type and make of a source of the input signal.

7. The method of claim 6, wherein the generating comprises retrieving a compensation voltage from a memory based on the type and make of the source.

8. The method of claim 7, wherein the compensation signal is a compensation voltage, and wherein the applying comprises turning on a number of current sinks to provide a voltage drop substantially equal to the compensation voltage.

9. The method of claim 6, wherein:

the source of the input signal comprises an integrated circuit; and

the type and make of the source comprises a type and make of the integrated circuit.