Multi-terminal harmonic oscillator integrated circuit with frequency calibration and frequency configuration

• US 7,679,463 B2
• Filed: 05/23/2007
• Issued: 03/16/2010
• Est. Priority Date: 03/22/2004
• Status: Active Grant

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Mobius Microsystems, Inc. (Renesas Electronics Corporation)
• Inventors: Carichner, Gordon, Marsman, Eric David, McCorquodale, Michael Shannon, Pernia, Scott Michael, Kubba, Sundus, O'Day, Justin
• Primary Examiner(s): Pascal; Robert
• Assistant Examiner(s): JOHNSON, RYAN
• Application Number:
  US11/805,368
• Publication Number:
  US 20070222528A1
• Time in Patent Office: 1,028 Days
• Field of Search: 331/44, 331/179, 331/34, 331/68, 331/108.C, 331/108.D, 331/117.R, 331/117.FE, 331/167, 331/116.R, 331/116.FE, 331/116.M, 331/154, 331/156, 331/158
• US Class Current: 331/108.00C
• CPC Class Codes: H03B 2200/0038 including a current mirror
• CPC Class Codes: H03B 2201/025 the means being an electronic switch for switching in or out oscillator elements
• CPC Class Codes: H03B 5/1212 the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair
• CPC Class Codes: H03B 5/1221 the amplifier comprising multiple amplification stages connected in cascade
• CPC Class Codes: H03B 5/1228 the amplifier comprising one or more field effect transistors
• CPC Class Codes: H03B 5/124 the means comprising a voltage dependent capacitance
• CPC Class Codes: H03J 2200/10 Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03L 1/022 by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature H03L1/021 takes precedence
• CPC Class Codes: H03L 1/023 by using voltage variable capacitance diodes
• CPC Class Codes: H03L 7/089 the phase or frequency detector generating up-down pulses H03L7/087 takes precedence

Abstract

Exemplary embodiments of the invention provide a reference harmonic oscillator integrated circuit having three or more terminals, with systems and methods for calibrating the harmonic oscillator to a selected first frequency using a limited number of terminals. An exemplary apparatus comprises: a reference harmonic oscillator, a first terminal to receive a supply voltage, a second terminal to receive a ground potential, a third terminal to provide an output signal having an output frequency, and may also include a fourth terminal. One of the first, second, third or fourth terminals is further adapted for input of a calibration of the first frequency. The exemplary apparatus may enter calibration and testing modes in response to various commands such as a calibration mode signal, and may also be configured through one of the terminals for output frequency selection, spread-spectrum output, and output voltage levels.

Claims

1. An apparatus comprising:

a reference harmonic oscillator to generate a first signal having a first frequency;

a first terminal to receive a supply voltage;

a second terminal to receive a ground potential; and

a third terminal to provide an output signal having an output frequency;

wherein one of the first, second or third terminals further is to receive input of a calibration of the first frequency and wherein one of the first, second or third terminals further is to receive input of a calibration mode signal having a frequency greater than a predetermined threshold to enter a calibration mode.

2. The apparatus of claim 1, wherein one of the first, second or third terminals further is to receive input of a command to enter a testing mode.

3. The apparatus of claim 2, wherein one of the first, second or third terminals further is to output a test parameter generated in the testing mode.

4. The apparatus of claim 3, wherein the test parameter is at least one of the following parameters:

a control voltage level, a node voltage at a selected temperature, a current level, a bandgap voltage level, a bias voltage level, or a transconductance bias current level.

5. The apparatus of claim 1, wherein the calibration input is a reference signal having a reference frequency.

6. The apparatus of claim 5, further comprising:

a frequency calibration circuit couplable to the harmonic oscillator, the frequency calibration circuit to receive the reference signal as the calibration input.

7. The apparatus of claim 1, wherein the calibration input is a first determination that the output frequency is higher than a reference frequency or a second determination that the output frequency is lower than the reference frequency.

8. The apparatus of claim 7, further comprising:

a reactance modulator circuit couplable to the harmonic oscillator, the reactance modulator circuit to receive the first determination or the second determination as the calibration input.

9. The apparatus of claim 1, wherein the calibration input is a plurality of calibration coefficients.

10. The apparatus of claim 9, further comprising:

a coefficient register couplable to the harmonic oscillator, the coefficient register to store the plurality of calibration coefficients as the calibration input.

11. The apparatus of claim 10, further comprising:

a plurality of switchable reactance modules couplable to the harmonic oscillator, wherein the plurality of calibration coefficients provide differential switching of the plurality of switchable reactance modules to the harmonic oscillator for first frequency selection or output frequency selection.

12. The apparatus of claim 1, wherein one of the first, second or third terminals further is to receive input of a configuration for selection of the output frequency.

13. The apparatus of claim 12, wherein the configuration input is a divide ratio for output frequency selection.

14. The apparatus of claim 12, wherein the configuration input is a spread-spectrum selection.

15. The apparatus of claim 12, wherein the configuration input is an output voltage level selection.

16. The apparatus of claim 1, wherein the calibration mode signal further has a predetermined sequence to enter the calibration mode.

17. The apparatus of claim 1, wherein one of the first, second or third terminals further is to respond within a predetermined period of time to the calibration mode signal to enter the calibration mode.

18. The apparatus of claim 1, wherein one of the first, second or third terminals further is to respond to the calibration mode signal input during a predetermined period of time and further is not to respond to the calibration mode signal subsequent to the predetermined period of time.

19. The apparatus of claim 1, further comprising:

a memory; and

wherein the apparatus further is to enter a test mode when a predetermined value is held in a register of the memory.

20. The apparatus of claim 19, wherein the apparatus further is to enter a reference mode when an additional predetermined value is held in the register of the memory.

21. The apparatus of claim 19, wherein the apparatus further is to enter a frequency configuration mode when an additional predetermined value is held in the register of the memory.

22. The apparatus of claim 1, wherein the first, second and third terminals each comprise at least one of the following:

an integrated circuit package pin or lead;

an integrated circuit input/output pad;

or an integrated circuit input or output driver.

23. The apparatus of claim 1, wherein the third terminal is coupled to the harmonic oscillator through at least one of the following circuits:

a voltage regulator circuit;

a frequency divider circuit;

a square-wave generator circuit;

a phase-locked loop circuit;

a delay-locked loop circuit;

a frequency-locked loop circuit;

an injection-locked loop circuit;

an inverter;

a buffer circuit;

a switching circuit;

an input driver circuit;

an output driver circuit.

24. The apparatus of claim 1, wherein the third terminal is coupled to the harmonic oscillator through a locking circuit, the locking circuit comprising at least one frequency divider circuit, the locking circuit to receive the first signal and generate the output signal having the output frequency as a rational multiple or rational fraction of the first frequency.

25. The apparatus of claim 1, wherein the reference harmonic oscillator is comprised of at least one inductor and at least one capacitor.

26. The apparatus of claim 1, wherein the reference harmonic oscillator is a microelectromechanical (MEMS) resonator.

27. The apparatus of claim 1, wherein the first, second and third terminals are the only input or output terminals of the apparatus.

28. The apparatus of claim 1, further comprising:

a fourth terminal to receive an enable signal.

29. An apparatus comprising:

a unitary integrated circuit comprising a reference harmonic oscillator and at most four terminals;

the reference harmonic oscillator to generate a first signal having a first frequency;

a first terminal of the four terminals to receive a supply voltage;

a second terminal of the four terminals to receive a ground potential;

a third terminal of the four terminals to provide an output signal having an output frequency, to provide output of digital data and analog data, and to receive input of digital data and analog data, wherein the input digital data comprises a calibration input of the first frequency; and

a fourth terminal of the four terminals to receive an enable signal, to receive a calibration mode signal, and to receive a digital clock input signal to synchronize digital data input for the third terminal.

30. The apparatus of claim 29, wherein one of the third or fourth terminals further is to receive input of a command to enter a testing mode.

31. The apparatus of claim 30, wherein the third terminal further is to output a test parameter generated in the testing mode.

32. The apparatus of claim 31, wherein the test parameter is at least one of the following parameters:

a control voltage level, a node voltage at a selected temperature, a current level, a bandgap voltage level, a bias voltage level, or a transconductance bias current level.

33. The apparatus of claim 29, wherein the third or fourth terminal further is to provide a selected input or output function.

34. The apparatus of claim 29, wherein the calibration input is a reference signal having a reference frequency.

35. The apparatus of claim 34, further comprising:

a frequency calibration circuit couplable to the harmonic oscillator, the frequency calibration circuit to receive the reference signal as the calibration input.

36. The apparatus of claim 29, wherein the calibration input is a first determination that the output frequency is higher than a reference frequency or a second determination that the output frequency is lower than the reference frequency.

37. The apparatus of claim 36, further comprising:

a reactance modulator circuit couplable to the harmonic oscillator, the reactance modulator circuit to receive the first determination or the second determination as the calibration input.

38. The apparatus of claim 29, wherein the calibration input is a plurality of calibration coefficients.

39. The apparatus of claim 38, further comprising:

a coefficient register couplable to the harmonic oscillator, the coefficient register to store the plurality of calibration coefficients as the calibration input.

40. The apparatus of claim 39, further comprising:

a plurality of switchable reactance modules couplable to the harmonic oscillator, wherein the plurality of calibration coefficients provide differential switching of the plurality of switchable reactance modules to the harmonic oscillator for first frequency selection or output frequency selection.

41. The apparatus of claim 29, wherein the third terminal further is to receive input of configuration digital data for selection of the output frequency.

42. The apparatus of claim 41, wherein the configuration digital data is a divide ratio for output frequency selection.

43. The apparatus of claim 41, wherein the configuration digital data is a spread-spectrum selection.

44. The apparatus of claim 41, wherein the configuration digital data is an output voltage level selection.

45. The apparatus of claim 29, wherein a calibration circuit coupled to the fourth terminal is to respond to the calibration mode signal to enter a calibration mode.

46. The apparatus of claim 45, wherein the calibration mode signal is an input voltage level greater than an operating voltage level.

47. The apparatus of claim 45, wherein the calibration mode signal is an input voltage level lower than a ground potential.

48. The apparatus of claim 45, wherein the calibration mode signal is an input signal having a frequency greater than a predetermined threshold.

49. The apparatus of claim 45, wherein the calibration mode signal is an input signal having a predetermined sequence.

50. The apparatus of claim 45, wherein the calibration circuit is to respond within a predetermined period of time to the calibration mode signal comprising an input signal having a predetermined sequence to enter a calibration mode.

51. The apparatus of claim 45, wherein the calibration circuit is to respond to the calibration mode signal input during a predetermined period of time and further is not to respond to the calibration mode signal subsequent to the predetermined period of time.

52. The apparatus of claim 29, further comprising:

a memory; and

wherein the apparatus is to enter a test mode when a predetermined value is held in a register of the memory.

53. The apparatus of claim 52, wherein the apparatus further is to enter a reference mode when an additional predetermined value is held in the register of the memory.

54. The apparatus of claim 52, wherein the apparatus further is to enter a frequency configuration mode when an additional predetermined value is held in the register of the memory.

55. The apparatus of claim 29, wherein the first, second, third and fourth terminals each comprise at least one of the following:

an integrated circuit package pin or lead;

an integrated circuit input/output pad;

or an integrated circuit input or output driver.

56. The apparatus of claim 29, wherein the third terminal is coupled to the reference harmonic oscillator through at least one of the following circuits:

a voltage regulator circuit;

a frequency divider circuit;

a square-wave generator circuit;

a phase-locked loop circuit;

a delay-locked loop circuit;

a frequency-locked loop circuit;

an injection-locked loop circuit;

an inverter;

a buffer circuit;

a switching circuit;

an input driver circuit;

an output driver circuit.

57. The apparatus of claim 29, wherein the third terminal is coupled to the reference harmonic oscillator through a locking circuit, the locking circuit comprising at least one frequency divider circuit, the locking circuit to receive the first signal and generate the output signal having the output frequency as a rational multiple or rational fraction of the first frequency.

58. The apparatus of claim 29, wherein the reference harmonic oscillator is comprised of at least one inductor and at least one capacitor.

59. The apparatus of claim 29, wherein the reference harmonic oscillator is a microelectromechanical (MEMS) resonator.

60. A method of providing a frequency calibration to the apparatus of claim 29, the method comprising:

providing the calibration mode signal to the fourth terminal for the apparatus to enter a calibration mode; and

providing a calibration digital data input to the third terminal; and

providing the digital clock input signal to synchronize the calibration digital data input for the third terminal.

61. An apparatus comprising:

a unitary integrated circuit comprising a reference harmonic oscillator and at most five terminals;

the reference harmonic oscillator to generate a first signal having a first frequency;

a first terminal of the five terminals to receive a supply voltage;

a second terminal of the five terminals to receive a ground potential;

a third terminal of the five terminals to provide an output signal having an output frequency, to receive input of digital data and to provide output of digital data, wherein the input digital data comprises a calibration input of the first frequency;

a fourth terminal of the five terminals to receive input of analog data and to provide output of analog data; and

a fifth terminal of the five terminals to receive an enable signal, to receive a calibration mode signal, and to receive a digital clock input signal to synchronize digital data input for the third terminal.

62. The apparatus of claim 61, wherein one of the third, fourth or fifth terminals further is to receive input of a command to enter a testing mode.

63. The apparatus of claim 62, wherein one of the third or fourth terminals further is to output a test parameter generated in the testing mode.

64. The apparatus of claim 63, wherein the test parameter is at least one of the following parameters:

a control voltage level, a node voltage at a selected temperature, a current level, a bandgap voltage level, a bias voltage level, or a transconductance bias current level.

65. The apparatus of claim 61, wherein the calibration input is a reference signal having a reference frequency.

66. The apparatus of claim 61, wherein the calibration input is a first determination that the output frequency is higher than a reference frequency or a second determination that the output frequency is lower than the reference frequency.

67. The apparatus of claim 61, wherein the calibration input is a plurality of calibration coefficients.

68. The apparatus of claim 61, wherein one of the third or fifth terminals further is to receive input of a configuration for selection of the output frequency, and wherein the configuration input is at least one of the following:

a divide ratio for output frequency selection, a spread-spectrum selection, or an output voltage level selection.

69. The apparatus of claim 61, wherein a calibration circuit coupled to the fourth terminal is to respond to the calibration mode signal to enter a calibration mode, and wherein the calibration mode signal is at least one of the following:

an input voltage level greater than an operating voltage level, an input voltage level lower than a ground potential, an input signal having a frequency greater than a predetermined threshold, an input signal having a predetermined sequence, or an input signal having a predetermined sequence within a predetermined period of time.

70. The apparatus of claim 61, further comprising:

a memory; and

wherein the apparatus is to enter a test mode when a first predetermined value is held in a first register of the memory and to enter a reference mode when a second predetermined value is held in the first register of the memory.

71. The apparatus of claim 70, wherein the apparatus is to enter a frequency configuration mode when an additional predetermined value is held in a second register of the memory.

72. The apparatus of claim 61, wherein the first, second, third, fourth and fifth terminals each comprise at least one of the following:

an integrated circuit package pin or lead;

an integrated circuit input/output pad;

or an integrated circuit input or output driver.

73. The apparatus of claim 61, wherein the third terminal is coupled to the reference harmonic oscillator through at least one of the following circuits:

a voltage regulator circuit;

a frequency divider circuit;

a square-wave generator circuit;

a phase-locked loop circuit;

a delay-locked loop circuit;

a frequency-locked loop circuit;

an injection-locked loop circuit;

an inverter;

a buffer circuit;

a switching circuit;

an input driver circuit;

an output driver circuit.

74. The apparatus of claim 61, wherein the third terminal is coupled to the reference harmonic oscillator through a locking circuit, the locking circuit comprising at least one frequency divider circuit, the locking circuit to receive the first signal and generate the output signal having the output frequency as a rational multiple or rational fraction of the first frequency.

75. A method of frequency calibration and testing of a unitary integrated circuit comprising a reference harmonic oscillator and at most four terminals, the method comprising:

providing a supply voltage to a first terminal of the four terminals;

providing a ground potential to a second terminal of the four terminals;

providing an enable signal to a third terminal of the four terminals;

providing a calibration mode signal to the third terminal for the unitary integrated circuit to enter a calibration mode;

receiving an output signal having an output frequency from a fourth terminal of the four terminals;

providing a digital clock input signal to the third terminal to synchronize digital data input to the fourth terminal;

receiving digital output data and analog output data from the fourth terminal;

providing digital input data and analog input data to the fourth terminal, wherein the digital input data comprises a calibration input or a configuration input of the output frequency.

76. The method of claim 75, wherein the calibration mode signal comprises at least one of the following:

an input voltage level greater than an operating voltage level, an input voltage level lower than a ground potential, an input signal having a frequency greater than a predetermined threshold, an input signal having a predetermined sequence, or an input signal having a predetermined sequence within a predetermined period of time.

77. The method of claim 75, further comprising:

determining whether the harmonic oscillator has been calibrated.

78. The method of claim 75, wherein the calibration input is at least one of the following:

a reference signal having a reference frequency;

a first determination that the output frequency is higher than a reference frequency;

a second determination that the output frequency is lower than the reference frequency;

or a plurality of calibration coefficients.

79. The method of claim 75, wherein the configuration input is at least one of the following:

a divide ratio for output frequency selection, a spread-spectrum selection, or an output voltage level selection.

80. A system for providing frequency calibration to a unitary integrated circuit comprising a reference oscillator and at most four terminals, the integrated circuit providing an output signal having an output frequency, the system comprising:

a user interface;

a reference signal generator; and

a first output couplable to the integrated circuit for providing a supply voltage to a first terminal of the four terminals;

a second output couplable to the integrated circuit for providing a ground potential to a second terminal of the four terminals;

a first combined input and output couplable to the integrated circuit for receiving an output signal having an output frequency from a third terminal of the four terminals, for receiving digital output data and analog output data from the third terminal, and for providing digital input data and analog input data to the third terminal, wherein the digital input data comprises a calibration input or a configuration input of the output frequency;

a second combined input and output couplable to the integrated circuit for providing an enable signal to a fourth terminal of the four terminals, for providing a calibration mode signal to the fourth terminal for the unitary integrated circuit to enter a calibration mode; and

for providing a digital clock input signal to the fourth terminal to synchronize digital data input to the third terminal; and

a control circuit coupled to the user interface and to the reference signal generator, the control circuit to generate the calibration mode signal and the calibration input or the configuration input for frequency modification.

81. The system of claim 80, wherein the control circuit further is to provide the calibration input as a reference signal having a reference frequency generated by the reference signal generator.

82. The system of claim 80, wherein the control circuit further comprises a calibration comparator to provide the calibration input as a first determination that the output frequency is higher than a reference frequency or as a second determination that the output frequency is lower than the reference frequency.

83. The system of claim 80, wherein the control circuit further comprises a reactance modulator to provide the calibration input as a plurality of calibration coefficients.

84. The system of claim 80, wherein the control circuit further is to provide the configuration input as at least one of the following:

a divide ratio for output frequency selection, a spread-spectrum selection, or an output voltage level selection.

85. The system of claim 80, wherein the control circuit further is to provide the calibration mode signal as at least one of the following:

an input voltage level greater than an operating voltage level, an input voltage level lower than a ground potential, an input signal having a frequency greater than a predetermined threshold, an input signal having a predetermined sequence, or an input signal having a predetermined sequence within a predetermined period of time.