Liquid crystal display device and fabricating method thereof

• US 7,679,699 B2
• Filed: 06/29/2005
• Issued: 03/16/2010
• Est. Priority Date: 12/31/2004
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Ahn, Byung Chul, Lim, Byoung Ho, Ahn, Jae Jun
• Primary Examiner(s): Nelms; David
• Assistant Examiner(s): Chien; Lucy P
• Application Number:
  US11/168,554
• Publication Number:
  US 20060146213A1
• Time in Patent Office: 1,721 Days
• Field of Search: None
• US Class Current: 349/114
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/136231 for reducing the number of lithographic steps
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence

Abstract

A liquid crystal display device, including: first and second substrates; a gate line on the first substrate; a data line crossing the gate line defining a pixel area with a gate insulating film therebetween; a thin film transistor including a gate electrode, a source electrode, a drain electrode, and a semiconductor layer with a channel between the source electrode and the drain electrode; a common line in parallel to the gate line on the first substrate; a common electrode extending from the common line into the pixel area; and a pixel electrode on the gate insulating film in the pixel area, wherein the drain electrode overlaps with the pixel electrode to connect to the pixel electrode; and wherein the semiconductor layer is removed from an area where it overlaps a transparent conductive film.

Claims

1. A liquid crystal display device, comprising:

first and second substrates;

a gate line on the first substrate;

a data line crossing the gate line defining a pixel area with a gate insulating film therebetween;

a thin film transistor including a gate electrode, a source electrode, a drain electrode, and a semiconductor layer with a channel between the source electrode and the drain electrode;

a common line in parallel to the gate line on the first substrate;

a common electrode extending from the common line into the pixel area;

a pixel electrode on the gate insulating film in the pixel area; and

a storage capacitor where the drain electrode overlaps a portion of the common electrode, wherein the drain electrode overlaps with the pixel electrode to connect to the pixel electrode;

wherein the semiconductor layer is removed from an area where it overlaps a transparent conductive film, and the common electrode includes a horizontal part overlapped with the drain electrode and a plurality of finger parts extending from the horizontal part and connected to the common line, wherein the pixel electrode connects to the drain electrode where the drain electrode overlaps the common electrode.

2. The device as claimed in claim 1, wherein the gate line and the common line have at least two conductive layers and the common electrode is formed by an extension of a transparent conductive layer of the common line.

3. The device as claimed in claim 2, wherein the at least two conductive layers has the transparent conductive layer.

4. The device as claimed in claim 1, wherein the pixel electrode overlaps with the common line.

5. The device as claimed in claim 1, wherein the gate line and the common line are formed of a metal layer.

6. The device as claimed in claim 1, wherein the storage capacitor further includes a semiconductor layer at the overlapping portion between the drain electrode and the gate insulating film.

7. The device as claimed in claim 1, further comprising:

a pad connected to at least one of the gate line, the common line, and the data line,

wherein the pad includes;

a lower pad electrode on the first substrate; and

an upper pad electrode in a contact hole passing through the gate insulating film to expose the lower pad electrode and connected to the lower pad electrode.

8. The device as claimed in claim 7, wherein the lower pad electrode is connected to at least one of the gate line and the common line.

9. The device as claimed in claim 7, further comprising:

a data link extending from the lower pad electrode so as to overlap the data line; and

a contact electrode in a second contact hole passing through the gate insulating film to expose the data link, thereby connecting the data link to the data line.

10. The device as claimed in claim 9, wherein the contact hole with the upper pad electrode extends along the data link to be integral with the second contact hole, and the upper pad electrode is integral with the contact electrode.

11. The device as claimed in claim 9, wherein the upper pad electrode and the contact electrode are formed of a transparent conductive layer bordering with the gate insulating film and enclosing the corresponding hole.

12. The device as claimed in claim 9, wherein a contact portion between the data line and the contact electrode is within an area to be sealed by a sealant upon joining of the first substrate with the second substrate.

13. The device as claimed in claim 10, wherein a contact portion between the data line and the contact electrode is within an area to be sealed by a sealant upon joining of the first substrate with the second substrate.

14. The device as claimed in claim 1, further comprising:

a data pad formed of a transparent conductive layer in the contact hole passing through the gate insulating film connected to the data line,

wherein the data pad borders with the gate insulating film and encloses the contact hole.

15. The device as claimed in claim 1, further comprising a data pad formed of a transparent conductive layer on the gate insulating film connected to the data line.

16. The device as claimed in claim 14, wherein the data line is within an area to be sealed by a sealant upon joining of the first substrate and the second substrate.

17. The device as claimed in claim 15, wherein the data line is within an area to be sealed by a sealant upon joining of the first substrate and the second substrate.

18. The device as claimed in claim 1, wherein the channel of the thin film transistor includes a surface layer oxidized by a plasma surface treatment.

19. The device as claimed in claim 1, wherein the data line, the source electrode, and the drain electrode have a source and drain metal pattern.

20. The device as claimed in claim 19, wherein the semiconductor layer and the source and drain metal pattern together have a shape.

21. The device as claimed in claim 7, further comprising a protective film on the first substrate where the protective film has an opening at a pad area.

22. The device as claimed in claim 21, further comprising an alignment film on the protective film.

23. The device as claimed in claim 22, wherein the protective film has the same pattern as the alignment film.

24. The device as claimed in claim 14, further comprising a protective film on the first substrate where the protective film has an opening at a pad area.

25. The device as claimed in claim 24, further comprising an alignment film on the protective film.

26. The device as claimed in claim 25, wherein the protective film has the same pattern as the alignment film.

27. The device as claimed in claim 15, further comprising a protective film on the first substrate where the protective film has an opening at a pad area.

28. The device as claimed in claim 27, further comprising an alignment film on the protective film.

29. The device as claimed in claim 28, wherein the protective film has the same pattern as the alignment film.

30. The device as claimed in claim 7, further comprising a protective film on the first substrate, the protective film has the same pattern as the second substrate and is opened at a pad area.

31. The device as claimed in claim 14, further comprising a protective film on the first substrate, the protective film has the same pattern as the second substrate and is opened at a pad area.

32. The device as claimed in claim 15, further comprising a protective film on the first substrate, the protective film has the same pattern as the second substrate and is opened at a pad area.

33. The device as claimed in claim 1, further comprising a liquid crystal layer between the first and second substrates.

34. A method of fabricating a liquid crystal display device, comprising:

providing first and second substrates;

a first mask process of forming a first mask pattern group including a gate line, a gate electrode, a common line, and a common electrode on the first substrate;

a second mask process including forming a gate insulating film on the first mask pattern group and a semiconductor layer, defining a pixel hole passing through the semiconductor layer at a pixel area, and forming a pixel electrode in the pixel hole; and

a third mask process including forming a source/drain metal pattern including a data line crossing the gate line to define the pixel area, a source electrode, and a drain electrode on the first substrate, and exposing an active layer of the semiconductor pattern to define a channel between the source electrode and the drain electrode wherein the drain electrode is overlapped with a portion of the common electrode to form a storage capacitor, and the common electrode includes a horizontal part overlapped with the drain electrode and a plurality of finger parts extending from the horizontal part and connected to the common line, and wherein the drain electrode overlaps with the pixel electrode to connect to the pixel electrode where the drain electrode overlaps the common electrode.

35. The method as claimed in claim 34, wherein the gate line, the gate electrode, and the common line have at least two conductive layers including a transparent conductive layer, and the common electrode is formed as an extension of the transparent conductive layer of the common line.

36. The method as claimed in claim 34, wherein the pixel electrode overlaps the common line.

37. The method as claimed in claim 34, wherein the first mask process comprises:

forming the at least two conductive layer on the first substrate;

forming photo-resist patterns having a different thicknesses using photolithography using a partial transmitting mask;

forming the first mask pattern group including the common electrode by an etching using the photo-resist pattern; and

etching the common electrode to remain a transparent conductive layer.

38. The method as claimed in claim 34, wherein the third mask process includes the semiconductor layer to overlap with the pixel electrode.

39. The method as claimed in claim 38, wherein the semiconductor layer overlaps except for an overlapping portion between the source and drain pattern and the pixel electrode.

40. The method as claimed in claim 34, wherein the third mask process includes:

forming a source and drain metal pattern including a data line and a drain electrode being integral to the source electrode on the first substrate;

etching a semiconductor layer exposed through the source and drain metal pattern; and

exposing the active layer between the source electrode and the drain electrode and to define the channel.

41. The method as claimed in claim 34, wherein the third mask process includes:

forming a source and drain metal layer on the first substrate and forming photo-resist patterns having different thicknesses thereon;

patterning the source and drain metal layer using the photo-resist patterns including the data line and the drain electrode;

etching a semiconductor layer exposed through the photo-resist patterns; and

exposing the active layer between the source electrode and the drain electrode through the photo-resist patterns to form the channel.

42. The method as claimed in claim 34, wherein:

the first mask process further includes forming a lower pad electrode connected to at least one of the gate line and the common line, and

the second mask process further includes forming a contact hole for exposing the lower pad electrode and forming an upper pad electrode connected to the lower pad electrode in the contact hole.

43. The method as claimed in claim 34, wherein:

the first mask process further includes forming a data link and a lower pad electrode connected to the data line on the first substrate; and

the second mask process further includes forming first and second contact holes to expose the lower pad electrode and the data link, and forming an upper pad electrode connected to the lower pad electrode and a contact electrode connected to the data link and the data line in the corresponding contact hole.

44. The method as claimed in claim 43, wherein the first contact hole with the upper pad electrode extends along the data link to be integral to the second contact hole and the upper pad electrode is integral to the contact electrode.

45. The method as claimed in claim 42, wherein a transparent conductive pattern including at least one of the upper pad electrode and the contact electrode borders with the gate insulating film enclosing the corresponding hole.

46. The method as claimed in claim 43, wherein a transparent conductive pattern including at least one of the upper pad electrode and the contact electrode borders with the gate insulating film enclosing the corresponding hole.

47. The method as claimed in claim 43, wherein a contact area between the data line and the contact electrode is within an area to be sealed by a sealant upon joining of the first substrate and the second substrate.

48. The method as claimed in claim 44, wherein a contact area between the data line and the contact electrode is within an area to be sealed by a sealant upon joining of the first substrate and the second substrate.

49. The method as claimed in claim 34, wherein the second mask process further includes:

forming a contact hole passing through the semiconductor layer and the gate insulating film and to overlap the data line; and

forming a pad connected to the data line in the contact hole.

50. The method as claimed in claim 49, wherein the pad borders with the gate insulating film enclosing the contact hole.

51. The method as claimed in claim 49, wherein the data line is within an area to be sealed by a sealant upon joining of the first substrate and the second substrate.

52. The method as claimed in claim 34, wherein the third mask process further includes surface treating the channel of the thin film transistor with plasma to oxidize the surface layer.

53. The method as claimed in claim 34, wherein the semiconductor layer and the source and drain metal pattern have a shape.

54. The method as claimed in claim 42, wherein the second mask process includes:

forming a photo-resist pattern on the semiconductor layer;

forming the pixel hole and the contact hole using the photo-resist pattern as a mask;

forming a transparent conductive film on the photo-resist pattern, and forming the corresponding transparent conductive pattern in the pixel hole and the contact hole; and

removing the photo-resist pattern formed with the transparent conductive film.

55. The method as claimed in claim 54, wherein the semiconductor layer and the gate insulating film are over-etched such that the edges of the pixel hole and the contact hole are positioned under the photo-resist pattern.

56. The method as claimed in claim 54, further comprising a fourth mask process of forming a protective film on the first substrate and with an opening at a pad area.

57. The method as claimed in claim 54, further comprising forming the protective film on the first substrate with the source/drain metal pattern so as to have an opening in the protective film at a pad area.

58. The method as claimed in claim 54, further comprising:

forming the protective film on the first substrate with the source and drain metal pattern;

forming an alignment film on the protective film; and

removing the protective film at a pad area by an etching using the alignment film as a mask.

59. The method as claimed in claim 54, further comprising:

forming a protective film on the first substrate;

joining the second substrate to the first substrate by a sealant; and

removing the protective film at a pad area by an etching using the second substrate as a mask, the protective film having an opening.

60. The method as claimed in claim 43, wherein the second mask process includes:

forming a photo-resist pattern on the semiconductor layer;

forming the pixel hole and the contact hole using the photo-resist pattern as a mask;

forming a transparent conductive film on the photo-resist pattern, and forming the corresponding transparent conductive pattern in the pixel hole and the contact hole; and

removing the photo-resist pattern formed with the transparent conductive film.

61. The method as claimed in claim 60, wherein the semiconductor layer and the gate insulating film are over-etched such that the edges of the pixel hole and the contact hole are positioned under the photo-resist pattern.

62. The method as claimed in claim 60, further comprising a fourth mask process of forming a protective film on the first substrate and with an opening at a pad area.

63. The method as claimed in claim 60, further comprising forming the protective film on the first substrate with the source/drain metal pattern so as to have an opening in the protective film at a pad area.

64. The method as claimed in claim 60, further comprising:

forming the protective film on the first substrate with the source and drain metal pattern;

forming an alignment film on the protective film; and

removing the protective film at a pad area by an etching using the alignment film as a mask.

65. The method as claimed in claim 60, further comprising:

forming a protective film on the first substrate;

joining the second substrate to the first substrate by a sealant; and

removing the protective film at a pad area by an etching using the second substrate as a mask, the protective film having an opening.

66. The method as claimed in claim 49, wherein the second mask process includes:

forming a photo-resist pattern on the semiconductor layer;

forming the pixel hole and the contact hole using the photo-resist pattern as a mask;

forming a transparent conductive film on the photo-resist pattern, and forming the corresponding transparent conductive pattern in the pixel hole and the contact hole; and

removing the photo-resist pattern formed with the transparent conductive film.

67. The method as claimed in claim 66, wherein the semiconductor layer and the gate insulating film are over-etched such that the edges of the pixel hole and the contact hole are positioned under the photo-resist pattern.

68. The method as claimed in claim 66, further comprising a fourth mask process of forming a protective film on the first substrate and with an opening at a pad area.

69. The method as claimed in claim 66, further comprising forming the protective film on the first substrate with the source/drain metal pattern so as to have an opening in the protective film at a pad area.

70. The method as claimed in claim 66, further comprising:

forming the protective film on the first substrate with the source and drain metal pattern;

forming an alignment film on the protective film; and

removing the protective film at a pad area by an etching using the alignment film as a mask.

71. The method as claimed in claim 66, further comprising:

forming a protective film on the first substrate;

joining the second substrate to the first substrate by a sealant; and

removing the protective film at a pad area by an etching using the second substrate as a mask, the protective film having an opening.

72. The method as claimed in claim 34, further comprising forming a liquid crystal layer between the first and second substrates.