Column select multiplexer circuit for a domino random access memory array

• US 7,679,949 B1
• Filed: 06/30/2008
• Issued: 03/16/2010
• Est. Priority Date: 11/14/2005
• Status: Active Grant

• Current Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Original Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Inventors: Masleid, Robert Paul
• Primary Examiner(s): PHUNG, ANH K
• Application Number:
  US12/165,432
• Time in Patent Office: 624 Days
• Field of Search: 365/154, 365/189.02, 365/156, 365/230.05
• US Class Current: 365/154
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction

Abstract

A column select multiplexer circuit for a domino random access memory array including a plurality of column selector circuits for selecting a column from a plurality of columns of static random access memory cells.

Claims

1. A column select multiplexer circuit for a domino random access memory array, comprising:

a plurality of column selector circuits for selecting a plurality of columns of static random access memory cells (SRAM cells), wherein each of said plurality of column selector circuits comprises;

a bitline precharge circuit for precharging a bitline and a bitline bar of a corresponding column of static random access memory cells (SRAM cells), said bitline precharge circuit coupled to said bitline and said bitline bar;

a first access n-type field effect transistor (NFET) coupled to said bitline and to a first node for accessing said bitline;

a second access NFET coupled to said bitline bar and to a second node for accessing said bitline bar;

a column select line coupled to said first and second access transistors that when activated selects said column of SRAM cells for reading and writing of a selected SRAM cell in said corresponding column of SRAM cells.

2. The column select multiplexer circuit of claim 1, wherein said bitline precharge circuit comprises:

a first p-type field effect transistor (PFET) cross-coupled to a second PFET through a first node coupled to said bitline and through second node coupled to said bitline bar;

a third PFET coupled to said bitline through said first node that when activated by a precharge signal precharges said bitline;

a fourth PFET coupled to said bitline bar through said second node that when activated by said precharge signal precharges said bitline bar.

3. The column select multiplexer circuit of claim 2, wherein said first access NFET comprises:

a source coupled to said first node;

a gate coupled to said column select line; and

a drain coupled to a column read/write access node.

4. The column select multiplexer circuit of claim 2, wherein said second access NFET comprises:

a source coupled to said second node;

a gate coupled to said column select line; and

a drain coupled to a column bar read/write access node.

5. The column select multiplexer circuit of claim 1, wherein said plurality of column selector circuits accesses at least eight columns of SRAM cells.

6. A column select multiplexer circuit for a domino random access memory array, comprising:

a first transistor coupled to a bitline of a first column of static random access memory cells (SRAM cells) and to a bitline precharge line for precharging said bitline;

a second transistor coupled to a bitline bar of said first column of SRAM cells and to said bitline precharge line for precharging said bitline bar;

a third transistor cross-coupled to a fourth transistor and coupled between said first and second transistors;

a first access transistor coupled to said bitline for read/write access of said bitline;

a second access transistor coupled to said bitline bar for read/write access of said bitline bar; and

a first column select line coupled to said first and second access transistors that when activated selects said first column of SRAM cells from a plurality of columns of SRAM cells each of which are selectable by said column select multiplexer circuit.

7. The column select multiplexer circuit of claim 6, wherein said first, second, third, and fourth transistors comprise a p-type field effect transistor (PFET).

8. The column select multiplexer circuit of claim 6, wherein said first access transistor and said second access transistor comprise a n-type field effect transistor (NFET).

9. The column select multiplexer circuit of claim 6, further comprising:

a fourth transistor coupled to a bitline of a second column of SRAM cells and to said bitline precharge line for precharging said bitline of said second column of SRAM cells;

a fifth transistor coupled to a bitline bar of said second column of SRAM cells and to said bitline precharge line for precharging said bitline bar of said second column of SRAM cells;

a third access transistor coupled to said bitline for read/write access of said bitline of said second column of SRAM cells;

a fourth access transistor coupled to said bitline bar for read/write access of said bitline bar of said second column of SRAM cells; and

a second column select line coupled to said third and fourth access transistors that when activated selects said second column of SPAM cells from said plurality of columns of SRAM cells.