Electronic circuit with a memory matrix

• US 7,679,952 B2
• Filed: 12/04/2006
• Issued: 03/16/2010
• Est. Priority Date: 12/07/2005
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Van Acht, Victor Martinus Gerardus, Mijiritskii, Andrei, Woerlee, Pierre Hermanus, Lambert, Nicolaas
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US12/096,226
• Publication Number:
  US 20080316805A1
• Time in Patent Office: 1,198 Days
• Field of Search: 365/163
• US Class Current: 365/163
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 2213/78 Array wherein the memory cells of a group share an access device, all the memory cells of the group having a common electrode and the access device being not part of a word line or a bit line driver
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type
• CPC Class Codes: H10B 63/82 the switching components having a common active material layer

Abstract

In an example embodiment, an electronic circuit comprises a memory matrix with rows and columns of memory cells. First row conductors are provided for each of the rows. Second row conductors correspond to pairs of rows, each successive row forming a respective pair with a preceding one of the rows, so that each pair overlaps with one row of the next pair. Column conductors are provided for each of the columns. Each of the memory cells comprises an access transistor, a node and a first and a second resistive memory element. The access transistor has a control electrode coupled to the first row conductor of the row of the memory cell, a main current channel coupled between the column conductor for the column of the memory cell and the node. The first and second the resistive memory element are coupled between the node and the second row conductors for the pairs of rows to which the memory cell belongs.

Claims

1. An electronic circuit, comprising a memory matrix comprising rows and columns of memory cells, the matrix comprising:

first row conductors for each of the rows, each first row conductor corresponding to a respective row of cells;

second row conductors corresponding to pairs of rows, each successive row forming a respective pair with a preceding one of the rows, so that each pair overlaps with one row of the next pair and;

column conductors for each of the columns,

wherein each of said memory cells comprises

an access transistor,

a node and

a first and second resistive memory element,

wherein the access transistor has a control electrode electrically coupled to the first row conductor of the row of the memory cell, a main current channel electrically coupled between the column conductor for the column of the memory cell and the node, the first and the second resistive memory element are electrically coupled between the node and the second row conductors for the pairs of rows to which the memory cell belongs.

2. An electronic circuit according to claim 1, wherein the access transistors are realized as vertical transistors, the main current channel extending transverse to the first and second row conductors and the column conductors, crossing the first row conductors so that the first row conductors act as gate electrodes for the access transistors, the column conductors and the second row conductors each lying in a respective plane on mutually opposite sides of the first row conductors, a region or regions comprising resistive memory material lying between the main current channels and the second row conductors.

3. An electronic circuit according to claim 2, wherein the column conductors comprise respective parallel doped areas in a semi-conductor substrate on which a remainder of the circuit is deposited.

4. An electronic circuit according to claim 2, wherein the second row conductors comprise respective parallel doped areas in a semi-conductor substrate on which a remainder of the circuit is deposited.

5. An electronic circuit according to claim 2, comprising intermediate conductive regions between respective ones of the main current channels and the region or regions comprising resistive memory material, the intermediate conductive regions being wider than the main current channels at least in a column direction.

6. An electronic circuit according to claim 1, comprising a read circuit coupled to the first and second row conductors and the column conductors, the read circuit being arranged to read a row of memory cells by:

driving a selection voltage level to the first row conductor of a selected one of the rows and a non-selection voltage level to the first row conductors of the remaining ones of the rows;

driving a mutually different first and second voltage to all second row conductors on mutually opposite sides of the selected one of the rows respectively;

measuring a current flowing through at least one of the column conductors.

7. An electronic circuit according to claim 1, comprising a write circuit coupled to the first and second row conductors and the column conductors, the write circuit being arranged to write to the resistive memory elements in a selected row of memory cells by:

driving a selection voltage level to the first row conductor of the selected row and a non-selection voltage level to the first row conductors of the remaining ones of the rows;

driving mutually different first and second voltages to second row conductors coupled to the first and second resistive memory elements of the memory cells in the selected row respectively;

driving data dependent voltages to the column conductors.

8. An electronic circuit according to claim 1, comprising a row selection circuit coupled to the first and second row conductors and arranged to erase information from the first and second resistive memory elements of the memory cells in a selected row by applying a voltage difference between the second row conductors coupled to the first and second resistive memory elements of the memory cells in the selected row.

9. An electronic circuit according to claim 1, wherein the first and second resistive memory elements comprise a fuse material or an anti-fuse material, which exhibits an irreversible change of resistance after applying a voltage above a threshold voltage across the resistive memory element.

10. An electronic circuit according to claim 1, wherein the first and second resistive memory elements comprise phase change material, which exhibits a resistance dependent on a write waveform applied across the resistive memory element.

11. An electronic circuit according to claim 1, wherein the first and second resistive memory elements comprise material with a hysteresis property, which exhibits a resistance dependent on a sign of a last write voltage applied across the resistive memory element.