Flash memory device and read method thereof
First Claim
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1. A read method of a flash memory device, comprising:
- precharging a bitline and a sense node;
developing the bitline and the sense node,wherein developing the bitline and the sense node comprises providing time for a precharge level transition;
recharging the sense node to compensate voltage loss of the sense node; and
after recharging the sense node, sensing a data value of a selected memory cell in response to the develop result of the sense node,wherein both the precharging operation and the recharging operation are always performed before the sensing operation is performed in each read cycle without regard to the data value of the selected memory cell.
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Abstract
A flash memory device and a read method thereof are provided. At a read operation, a sense node of a page buffer is developed while a bitline is developed and data of a selected memory cell is sensed based on the develop result of the sense node. For a develop period, voltage loss arising from the sense node is compensated fast and the compensated result is latched, which makes it possible to simplify the design and reduce a chip size.
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Citations
12 Claims
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1. A read method of a flash memory device, comprising:
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precharging a bitline and a sense node; developing the bitline and the sense node, wherein developing the bitline and the sense node comprises providing time for a precharge level transition; recharging the sense node to compensate voltage loss of the sense node; and after recharging the sense node, sensing a data value of a selected memory cell in response to the develop result of the sense node, wherein both the precharging operation and the recharging operation are always performed before the sensing operation is performed in each read cycle without regard to the data value of the selected memory cell. - View Dependent Claims (2, 3)
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4. A flash memory device comprising:
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a memory cell array including a plurality of memory cells disposed at intersections of bitlines and wordlines; and a page buffer circuit including a plurality of page buffers for sensing data stored in the memory cells, wherein each of the page buffers precharges a corresponding bitline and a corresponding sense node and develops the sense node while the bitline is developed and senses a data value of a memory cell connected to a selected bitline in response to the develop result of the sense node, wherein developing the bitline and the sense node comprises providing time for a precharge level transition; and wherein the page buffer recharges the sense node before sensing the data value, to compensate voltage loss of the sense node, and wherein the page buffer performs both the precharging operation and the recharging operation before the sensing operation is always performed in each read cycle without regard to the data value of the memory cell connected to the selected bitline. - View Dependent Claims (5)
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6. A flash memory device comprising:
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a memory cell array including a plurality of memory cells disposed at intersections of bitlines and wordlines; and a page buffer circuit including a plurality of page buffers for sensing data stored in the memory cells, wherein each of the page buffers comprises; a precharge circuit for precharging a corresponding bitline and a corresponding a sense node and developing the sense node while the bitline is developed; wherein developing the bitline and the sense node comprises providing time for a precharge level transition; and a sense and latch circuit for sensing and storing a data value of a memory cell connected to a selected bitline in response to the develop result of the sense node, wherein the page buffer recharges the sense node before sensing the data value, to compensate voltage loss of the sense node, and wherein the page buffer performs both the precharging operation and the recharging operation before the sensing operation is always performed in each read cycle without regard to the data value of the memory cell connected to the selected bitline. - View Dependent Claims (7, 8, 9, 10, 11, 12)
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Specification