Device coupled between serial busses using bitwise arbitration

• US 7,680,144 B2
• Filed: 09/12/2006
• Issued: 03/16/2010
• Est. Priority Date: 09/12/2006
• Status: Active Grant

• Current Assignee: Ademco Inc. (Resideo Technologies, Inc.)
• Original Assignee: Honeywell International Inc.
• Inventors: Nichols, Steven C.
• Primary Examiner(s): Ngo; Ricky
• Assistant Examiner(s): SINKANTARAKORN, PAWARIS
• Application Number:
  US11/519,622
• Publication Number:
  US 20080063006A1
• Time in Patent Office: 1,281 Days
• Field of Search: 370/431, 370/433, 370/437, 370445-451, 370/462
• US Class Current: 370/451
• CPC Class Codes: H04L 12/66 Arrangements for connecting between networks having differing types of switching systems, e.g. gateways

Abstract

First and second serial data busses are arranged so that simultaneous transmission on the respective bus of a dominant state by one node and a recessive state by other nodes results in the dominant state being detectable on the respective bus. Transitions from a first state to a second state signal the start of a bit on the first bus. Dominant and recessive states are detected on the first and second busses at first and second predetermined times after each transition. The states represent respective dominant and recessive bits of attempted messages transmitted by nodes of the first and second busses. The dominant state is transmitted on both busses after the first and second predetermined times if the dominant state was detected on one of the first and the second busses at the first and second predetermined times.

Claims

1. A method of communicating between first and second serial data busses, each bus comprising one or more nodes coupled via the respective data bus so that simultaneous transmission on the respective bus of a dominant state by at least one of the nodes and a recessive state by the other nodes results in the dominant state being detectable on the respective bus, the method comprising:

transmitting onto the first bus transitions from a first state to a second state, wherein the first and second states are complementary states selected from the dominant and recessive states, each of the transitions signaling the start of a bit on the first bus;

transmitting the transition onto the second bus synchronously with the transmission of transitions onto the first bus;

detecting dominant and recessive states on the first bus at a first predetermined time after each transition and on the second bus at a second predetermined time after each transition, the states representing respective dominant and recessive bits of attempted messages transmitted by nodes of the first and second busses, wherein the first and second predetermined times are less than a standard predetermined time after the transition that nodes of the first and second busses use to respectively detect the state of the first and second busses; and

transmitting the dominant state on both the first and second bus after the first and second predetermined times if the dominant state was detected on at least one of the first bus and the second bus at the respective first and second predetermined times.

2. The method of claim 1, further comprising ceasing transmission of bits onto the first and second busses by any of nodes of the first and second busses that were transmitting a recessive bit after the respective first and second predetermined times and detected a dominant bit after the respective first and second predetermined times.

3. A processor-readable medium, comprising:

a program storage medium configured with instructions for use by a device to perform the operations of claim 1.

4. The method of claim 1, wherein a device transmitting the transitions on to the first and second busses is established as a bit master on both the first and second busses, wherein a node of the first or second busses is arbitrarily selected as the bit master of the respective bus if the transmission is not detected for a predefined time period on the respective bus.

5. A method of communicating between first and second serial data busses, each bus comprising one or more nodes coupled via the respective data bus so that simultaneous transmission on the respective bus of a dominant state by at least one of the nodes and a recessive state by the other nodes results in the dominant state being detectable on the respective bus, the method comprising:

transmitting onto the first bus transitions from a first state to a second state, wherein the first and second states are complementary states selected from the dominant and recessive states, each of the transitions signaling the start of a bit on the first bus;

detecting dominant and recessive states on the first bus at a first predetermined time after each transition and on the second bus at a second predetermined time after each transition, the states representing respective dominant and recessive bits of attempted messages transmitted by nodes of the first and second busses;

detecting a synchronization signal of the second bus from an alternating current power signal of the second bus;

transmitting the dominant state on both the first and second bus after the first and second predetermined times if the dominant state was detected on at least one of the first bus and the second bus at the respective first and second predetermined times; and

wherein the transmission of the transition onto the first bus is in response to the synchronization signal of the second bus and causes bits to be transmitted onto the first bus at a slower rate than a maximum bit rate of nodes of the first bus.

6. A processor-readable medium, comprising a program storage medium configured with instructions for use by a device to perform the operations of claim 5.

7. The method of claim 5, wherein detecting the synchronization signal of the second bus from an alternating current power signal of the second bus comprises detecting the synchronization signal based on zero crossings of a voltage signal of the alternating current power line.

8. The method of claim 5, wherein a device transmitting the transitions on to the first bus is established as a bit master on the first bus, wherein a node of the first bus is arbitrarily selected as the bit master if the transmission is not detected for a predefined time period on the first bus.

9. An apparatus operable in a data processing arrangement that includes first and second serial data busses, each bus having one or more nodes coupled via the respective data bus so that simultaneous transmission on the respective bus of a dominant state by at least one of the nodes and a recessive state by the other nodes results in the dominant state being detectable on the respective bus, the apparatus comprising:

a first transceiver coupled to the first bus and capable of transmitting and receiving the dominant and recessive states via the first bus;

a second transceiver coupled to the second bus and capable of transmitting and receiving the dominant and recessive states via the second bus;

a synchronization detector coupled to an alternating current power line of the second bus, the synchronization detector providing a synchronization signal proportional to the frequency of the alternating current power line, the synchronization signal signaling the beginning of bit transmissions onto the second bus;

a processor coupled to the first and second transceivers and the synchronization detector, the processor operable via instructions to cause the apparatus to,

transmit, via the first transceiver, repeated transitions from a first state to a second state on the first bus in response to the synchronization signal of the second bus, wherein the first and second states are complementary states selected from the dominant and recessive states, and wherein the transmission of the transition onto the first bus in response to the synchronization signal of the second bus causes bits to be transmitted onto the first bus at a slower rate than a maximum bit rate of nodes of the first bus;

detect via the first transceiver dominant and recessive states on the first bus at a first predetermined time after each transition;

detect via the second transceiver dominant and recessive states on the second bus at a second predetermined time after each transition; and

transmit the dominant state on both the first and second bus after the first and second predetermined times if the dominant state was detected on either the first bus or the second bus at respective first and second predetermined times.

10. The apparatus of claim 9, wherein the synchronization detector provides the synchronization signal based on zero crossings of a voltage signal of the alternating current power line.

11. The apparatus of claim 9, wherein transmitting the transitions on to the first bus establishes the apparatus as a bit master on the first bus, wherein a node of the first bus is arbitrarily selected as the bit master if the transmission is not detected for a predefined time period on the first bus.

12. The apparatus of claim 9, wherein the first and second busses comprise thermostat wires.

13. The apparatus of claim 12, wherein transmitting the transitions on to the first and second busses establishes the apparatus as a bit master on the first and second busses, wherein a node of the first or second busses is arbitrarily selected as the bit master of the respective bus if the transmission is not detected for a predefined time period on the respective bus.

14. An apparatus operable in a data processing arrangement that includes first and second serial data busses, each bus having one or more nodes coupled via the respective data bus so that simultaneous transmission on the respective bus of a dominant state by at least one of the nodes and a recessive state by the other nodes results in the dominant state being detectable on the respective bus, the apparatus comprising:

a first transceiver coupled to the first bus and capable of transmitting and receiving the dominant and recessive states via the first bus;

a second transceiver coupled to the second bus and capable of transmitting and receiving the dominant and recessive states via the second bus;

a processor coupled to the first and second transceivers and operable via instructions to cause the apparatus to,

transmit, via the first transceiver, repeated transitions from a first state to a second state on the first bus, wherein the first and second states are complementary states selected from the dominant and recessive states;

detect via the first transceiver dominant and recessive states on the first bus at a first predetermined time after each transition;

detect via the second transceiver dominant and recessive states on the second bus at a second predetermined time after each transition; and

transmit the dominant state on both the first and second bus after the first and second predetermined times if the dominant state was detected on either the first bus or the second bus at respective first and second predetermined times, wherein the first predetermined time is less than a predetermined time after the transition that nodes of the first bus use to detect the state of the first bus.

15. The apparatus of claim 14, wherein the second predetermined time is less than a predetermined time after the transition that nodes of the second bus use to detect the state of the second bus.

16. The apparatus of claim 14, wherein processor causes the second transceiver to repeatedly transmit the transitions on the second bus synchronously with the transmission of the transitions onto the first bus.

17. The apparatus of claim 14, wherein the processor further causes the apparatus to transmit, via the second transceiver, the repeated transitions from the first state to the second state on the second bus.

18. The apparatus of claim 14, wherein the first and second busses comprise thermostat wires.