Spread spectrum clock generator having an adjustable delay line

• US 7,680,173 B2
• Filed: 06/30/2006
• Issued: 03/16/2010
• Est. Priority Date: 07/06/2005
• Status: Active Grant

• Current Assignee: ESS Technology Incorporated (Semiconductor Holding Corp.)
• Original Assignee: ESS Technology Incorporated (Semiconductor Holding Corp.)
• Inventors: Mallinson, Andrew Martin, Damphousse, Simon
• Primary Examiner(s): VO, DON NGUYEN
• Application Number:
  US11/479,537
• Publication Number:
  US 20070019711A1
• Time in Patent Office: 1,355 Days
• Field of Search: 375/130
• US Class Current: 375/130
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04B 15/02 Reducing interference from electric apparatus by means located at or near the interfering apparatus
• CPC Class Codes: H04B 2215/067 by modulation dispersion

Abstract

A system and method are provided for performing a spread spectrum clock generation, where the system includes self-adjusting delay line configured to spread the spectrum of a fixed circuit using a fixed clock frequency and a delay circuit configured to generate an adjustment signal to the delay line by adding or subtracting an addition delay per cycle, therefore causing a shift in the output clock frequency, wherein the amount of shift is proportional to the rate of addition or subtraction of delay.

Claims

1. A spread spectrum clock generation circuit comprising:

a delay line configured to spread the spectrum of a reference clock signal having a reference clock frequency;

a delay circuit configured to generate an adjustment signal to the delay line by adding a delay change to or subtracting the delay change from the delay line per cycle of the reference clock frequency, therefore causing a shift in the output clock frequency of the spread spectrum clock generation circuit, wherein the amount of shift is proportional to the rate of addition or subtraction of the delay change.

2. A circuit according to claim 1, where the delay circuit is configured to enable an optimum pattern of frequency shifts as a table of delay versus clock cycle.

3. A circuit according to claim 1 wherein the clock circuit generating the reference clock signal is one of a crystal and a phase locked loop (PLL) circuit.

4. The circuit of claim 1, wherein the delay circuit calculates the shift in output frequency as a percentage of a number of taps in the delay circuit corresponding to one period of the reference clock frequency.

5. The circuit of claim 1, wherein the delay circuit wraps around the delay line by a total delay corresponding to a period of the reference clock frequency.

6. The circuit of claim 1, wherein the delay circuit wraps in a forward direction around the delay line by a total delay corresponding to a period of the reference clock frequency.

7. The circuit of claim 1, wherein the delay circuit wraps in a backward direction around the delay line by a total delay corresponding to a period of the reference clock frequency.

8. The circuit of claim 1, further comprising:

a clock circuit generating the reference clock frequency; and

a system phase lock loop;

wherein the delay line and the delay circuit are between the clock circuit and the system phase lock loop.

9. The circuit of claim 1, further comprising:

a delta sigma modulator dithering a step size of taps in the delay line.

10. The circuit of claim 1, wherein the delay line includes duplicated taps that monitor a clock edge.

11. The circuit of claim 1, further comprising:

a reference clock circuit generating the reference clock signal as the reference clock frequency.

12. The circuit of claim 1, wherein the delay circuit wraps around the delay line by a total delay corresponding to a period of the reference clock frequency, and

wherein the delay line includes adaptive circuitry compensate for discontinuity responsive to the delay circuit wrapping around the delay line.