System with secure cryptographic capabilities using a hardware specific digital secret
First Claim
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1. A processor, comprising:
- a digital secret including a secret key used in a key-based cryptographic process, wherein the digital secret is stored within the processor, wherein the processor is configured to use the digital secret for both encryption and decryption, wherein the digital secret is calculated using an HMAC algorithm implemented on testing data, and wherein the testing data is associated with fabrication of the processor;
a cryptography engine configured to perform the key-based cryptographic process internally within the processor using the digital secret; and
internal memory configured to store data associated with the key-based cryptographic process, wherein the data includes at least one result of a calculation performed by the key-based cryptographic process.
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Abstract
A system with secure cryptographic capabilities using a hardware specific digital secret.
138 Citations
25 Claims
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1. A processor, comprising:
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a digital secret including a secret key used in a key-based cryptographic process, wherein the digital secret is stored within the processor, wherein the processor is configured to use the digital secret for both encryption and decryption, wherein the digital secret is calculated using an HMAC algorithm implemented on testing data, and wherein the testing data is associated with fabrication of the processor; a cryptography engine configured to perform the key-based cryptographic process internally within the processor using the digital secret; and internal memory configured to store data associated with the key-based cryptographic process, wherein the data includes at least one result of a calculation performed by the key-based cryptographic process. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A processor, comprising:
a secure cryptography unit, wherein the secure cryptography unit is configured to internally provide secure cryptographic capabilities as a functional unit within the processor, the secure cryptography unit including; a cryptography engine configured to perform a key-based cryptographic process; a digital secret accessible to the cryptography engine, wherein the digital secret includes a secret key used in the key-based cryptographic process, wherein the processor is configured to use the secret key for both encryption and decryption, wherein the digital secret is calculated using an HMAC algorithm implemented on testing data, and wherein the testing data is associated with fabrication of the processor; and internal memory configured to store data associated with the key-based cryptographic process, wherein the data includes at least one result of a calculation performed by the key-based cryptographic process. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A processor, comprising:
a secure hardware environment configured to provide core processing functionality, wherein the secure hardware environment includes; a secure cryptography unit configured to provide secure cryptographic capabilities as a functional unit within the secure hardware environment, wherein the secure cryptography unit is configured to facilitate performance of a key-based cryptographic process performed by the processor, wherein the key-based cryptographic process includes encryption using a digital secret and decryption using the digital secret, wherein the digital secret is calculated using an HMAC algorithm implemented on testing data, wherein the testing data is associated with fabrication of the processor, wherein the key-based cryptographic process further includes generating data, wherein the data includes at least one result of a calculation performed by the key-based cryptographic process. - View Dependent Claims (21, 22, 23, 24, 25)
Specification