Power management of non-volatile memory systems

• US 7,681,057 B2
• Filed: 08/07/2007
• Issued: 03/16/2010
• Est. Priority Date: 09/28/2001
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Lexar Media Incorporated (Micron Technology, Inc.)
• Inventors: Payne, Robert Edwin
• Primary Examiner(s): Lee; Thomas
• Assistant Examiner(s): TRAN, VINCENT HUY
• Application Number:
  US11/835,039
• Publication Number:
  US 20080215903A1
• Time in Patent Office: 952 Days
• Field of Search: 713/300, 713/320, 713/322, 326/93, 331/60
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

Methods and apparatus for placing a non-volatile memory systems in one of a number of power-down modes in response to events being monitored are useful in reducing power consumption of the non-volatile memory system. The power-down modes provide for successively less functionality, thus providing for successively less power consumption. A non-volatile memory system thus can respond to the events to place the system in a mode that permits the desired operation or a desired response time for subsequent operations while seeking to minimize power consumption.

Claims

1. A controller for a non-volatile memory system, comprising:

a system bus;

a power management system in communication with the system bus and comprising a clock oscillator adapted to selectively output a fundamental clock signal, a phase-locked loop adapted to selectively output a second clock signal in response to the fundamental clock signal, and a system clock control adapted to selectively distribute a system clock signal in response to the second clock signal;

a microprocessor in communication with the system bus;

a first interface in communication with the system bus and adapted for communication with a non-volatile memory device; and

a second interface in communication with the system bus and adapted for communication with a host system;

wherein the power management system is adapted to monitor events from sources including at least the first interface and the second interface;

wherein the power management system is further adapted to select one of a plurality of successive power-down modes in response to the events;

wherein, in a first power-down mode, the controller is adapted to provide for normal operation;

wherein, in a second power-down mode, the microprocessor is disabled;

wherein, in a third power-down mode, the system clock control is further disabled;

wherein the phase-locked loop is configured to receive the fundamental clock signal from the clock oscillator and to generate the second clock signal by directly multiplying the fundamental clock signal by a multiplication factor that is received at an input of the phase-locked loop; and

wherein the power management system is further adapted to alter the multiplication factor in response to one or more of the events.

2. The controller of claim 1, wherein the power management system further comprises:

a first power-down controller for generating a first enable signal for selectively enabling or disabling the microprocessor; and

a second power-down controller for generating a second enable signal for selectively enabling or disabling the system clock control.

3. The controller of claim 1, wherein, in a fourth power-down mode, the phase-locked loop is further disabled.

4. The controller of claim 3, wherein the power management system further comprises:

a first power-down controller for generating a first enable signal for selectively enabling or disabling the microprocessor;

a second power-down controller for generating a second enable signal for selectively enabling or disabling the system clock control; and

a third power-down controller for generating a third enable signal for selectively enabling or disabling the phase-locked loop.

5. The controller of claim 4, wherein the third power-down controller is adapted to enforce a delay when transitioning from the fourth power-down mode to the third power-down mode.

6. The controller of claim 3, wherein, in a fifth power-down mode, the clock oscillator is further disabled.

7. The controller of claim 6, wherein the power management system further comprises:

a first power-down controller for generating a first enable signal for selectively enabling or disabling the microprocessor;

a second power-down controller for generating a second enable signal for selectively enabling or disabling the system clock control;

a third power-down controller for generating a third enable signal for selectively enabling or disabling the phase-locked loop; and

a fourth power-down controller for generating a fourth enable signal for selectively enabling or disabling the clock oscillator.

8. The controller of claim 7, wherein the fourth power-down controller is adapted to enforce a delay when transitioning from the fifth power-down mode to the fourth power-down mode.

9. The controller of claim 1, wherein the first interface is further adapted for communication with a flash memory device.

10. The controller of claim 1, wherein the second interface is further adapted to present the logical characteristics of a disc storage device to the host system.

11. The controller of claim 1, further comprising a register coupled to the phase-locked loop and configured to store the multiplication factor.

12. The controller of claim 11, wherein the power management system is further adapted to alter the multiplication factor within the register in response to the one or more of the events while the phase-locked loop is enabled.

13. The controller of claim 1, wherein the power management system is further adapted to throttle operation of the microprocessor in response to one or more of the events while in the first power-down mode.

14. The controller of claim 1, wherein the power management system is adapted to throttle operation of the microprocessor by selectively cycling the microprocessor on and off in response to a first register value indicative of a desired ratio value of enabled cycles, a second register value indicative of a desired ratio value of disabled cycles, and a third register value indicative of a minimum number of consecutive cycles that the microprocessor must remain in either an enabled condition or a disabled condition.

15. The controller of claim 1, wherein the controller is coupled between the non-volatile memory and the host system.

16. A method of operating a non-volatile memory system, comprising:

monitoring events from at least one source;

placing the non-volatile memory system in a first power-down mode in response to one or more first events, wherein the first power-down mode permits normal operation of the non-volatile memory system;

placing the non-volatile memory system in a second power-down mode in response to one or more second events, wherein placing the non-volatile memory system in the second power-down mode comprises disabling a microprocessor of the non-volatile memory system;

receiving a fundamental clock signal and a multiplication factor at a phase-locked loop of the non-volatile memory system;

altering the multiplication factor in response to one or more of the monitored events;

generating a system clock signal at the phase-locked loop by directly multiplying the fundamental clock signal by the multiplication factor; and

placing the non-volatile memory system in a third power-down mode in response to one or more third events, wherein placing the non-volatile memory system in the third power-down mode comprises disabling distribution of the system clock signal of the non-volatile memory system.

17. The method of claim 16, wherein placing the non-volatile memory system in the third power-down mode in response to one or more third events further comprises placing the non-volatile memory in the second power-down mode if it is in the first power-down mode before placing the non-volatile memory in the third power-down mode.

18. The method of claim 16, further comprising placing the non-volatile memory system in a fourth power-down mode in response to one or more fourth events, wherein placing the non-volatile memory system in the fourth power-down mode comprises disabling generation of the system clock signal.

19. The method of claim 18, further comprising enforcing a delay when transitioning from the fourth power-down mode to the third power-down mode.

20. The method of claim 18, further comprising:

if the non-volatile memory system is in the first power-down mode, placing the non-volatile memory system in the second power-down mode and then placing the non-volatile memory system in the third power-down mode before placing the non-volatile memory system in the fourth power-down mode; and

if the non-volatile memory system is in the second power-down mode, placing the non-volatile memory system in the third power-down mode before placing the non-volatile memory system in the fourth power-down mode.

21. The method of claim 18, further comprising placing the non-volatile memory system in a fifth power-down mode in response to one or more fifth events, wherein placing the non-volatile memory system in the fifth power-down mode comprises disabling generation of a fundamental clock signal used to generate the system clock signal.

22. The method of claim 21, further comprising enforcing a delay when transitioning from the fifth power-down mode to the fourth power-down mode.

23. The method of claim 21, further comprising:

if the non-volatile memory system is in the first power-down mode, placing the non-volatile memory system in the second power-down mode then placing the non-volatile memory system in the third power-down mode then placing the non-volatile memory system in the fourth power-down mode before placing the non-volatile memory system in the fifth power-down mode;

if the non-volatile memory system is in the second power-down mode, placing the non-volatile memory system in the third power-down mode then placing the non-volatile memory system in the fourth power-down mode before placing the non-volatile memory system in the fifth power-down mode; and

if the non-volatile memory system is in the third power-down mode, placing the non-volatile memory system in the fourth power-down mode before placing the non-volatile memory system in the fifth power-down mode.

24. The method of claim 21, further comprising receiving the multiplication factor at the phase-locked loop from a register of the non-volatile memory system.

25. The method of claim 24, further comprising altering the multiplication factor within the register while generating the system clock signal.

26. The method of claim 16, further comprising presenting logical characteristics of a disc storage device to a host system while in the first or second power-down modes.

27. The method of claim 16, further comprising throttling operation of the microprocessor in response to one or more of the first events while in the first power-down mode.

28. The method of claim 16, wherein throttling operation of the microprocessor comprises selectively cycling the microprocessor on and off.

29. The method of claim 16, further comprising making a copy of an event signal that cannot be de-asserted by a source of the event generating the event signal and responding to the copy of the event signal in determining whether an event has occurred.