Capacitor layout technique for reduction of fixed pattern noise in a CMOS sensor
First Claim
Patent Images
1. An imager, comprising:
- a pixel array including pixels for converting light into electrical signals; and
a circuit for sampling signals produced by a pixel, the sampling circuit includingan input line for receiving signals produced by said pixel,a sample capacitor, anda switch for controllably coupling said sample capacitor to said input line;
wherein said sample capacitor is fabricated as a semiconductor device and further includesa front plate comprising a first conductive portion;
a first dielectric portion above and adjacent to said front plate;
a second dielectric portion below and adjacent to said front plate;
a first conductive structure surrounding said first and second dielectric portions, said conductive structure including a back plate of said capacitor;
a third dielectric portion above and adjacent to said first conductive structure;
a fourth dielectric portion below and adjacent to said first conductive structure; and
a second conductive structure surrounding said third and fourth portions.
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Abstract
A new capacitor architecture includes a front plate of the capacitor formed from a first polysilicon layer. The front plate is surrounded by a first dielectric layer and a second dielectric layer. The back plate of the capacitor is formed from one layer of a first two-layer conductive structure which surrounds the first dielectric layer and the second dielectric layer. The two-layer conductive structure is an equal potential structure and includes a conductive coupling between the two layers.
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Citations
32 Claims
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1. An imager, comprising:
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a pixel array including pixels for converting light into electrical signals; and a circuit for sampling signals produced by a pixel, the sampling circuit including an input line for receiving signals produced by said pixel, a sample capacitor, and a switch for controllably coupling said sample capacitor to said input line; wherein said sample capacitor is fabricated as a semiconductor device and further includes a front plate comprising a first conductive portion; a first dielectric portion above and adjacent to said front plate; a second dielectric portion below and adjacent to said front plate; a first conductive structure surrounding said first and second dielectric portions, said conductive structure including a back plate of said capacitor; a third dielectric portion above and adjacent to said first conductive structure; a fourth dielectric portion below and adjacent to said first conductive structure; and a second conductive structure surrounding said third and fourth portions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. An imager, comprising:
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a pixel array including pixels for converting light into electrical signals; and a circuit for sampling signals produced by a pixel, the sampling circuit including an input line for receiving signals produced by said pixel, a sample capacitor, and a switch for controllably coupling said sample capacitor to said input line; wherein said sample capacitor is fabricated as a semiconductor device and further includes a first plate; a first conductive structure surrounding and thereby shielding said first plate to reduce parasitic capacitance, said first conductive structure further comprising a second plate of said capacitor; and a second conductive structure surrounding and thereby shielding said first plate and said second plate to reduce parasitic capacitance. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23)
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24. An imager, comprising:
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a pixel array including pixels for converting light into electrical signals; a circuit for sampling signals produced by a pixel, the sampling circuit including an input line for receiving signals produced by said pixel, a sample capacitor, and a switch for controllably coupling said sample capacitor to said input line; wherein said sample capacitor is fabricated as a semiconductor device and further includes a first plate, a second plate, a first shield, said first shield including a first surface and a second surface, said first surface and said second surface being equal potential surfaces, and a second shield, said second shield including a third surface and a fourth surface, said third surface and said fourth surface being equal potential surfaces; wherein said first plate and said second plate are disposed to form two plates of said capacitor, said first surface and said second surface are disposed to shield said first plate to reduce parasitic capacitance, and said third surface and said fourth surface are disposed to shield said first plate and said second plate to reduce parasitic capacitance. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32)
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Specification