Method for manufacturing semiconductor device

• US 7,682,965 B2
• Filed: 11/27/2006
• Issued: 03/23/2010
• Est. Priority Date: 12/20/2005
• Status: Expired due to Fees

• Current Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Original Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Inventors: Lee, Han Choon, Kim, Sang Chul
• Primary Examiner(s): Le; Thao P.
• Application Number:
  US11/604,921
• Publication Number:
  US 20070141833A1
• Time in Patent Office: 1,212 Days
• Field of Search: 438/637, 257/E23.145
• US Class Current: 438/637
• CPC Class Codes: H01L 21/02074 the processing being a planarization of conductive layers
• CPC Class Codes: H01L 21/76886 Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances

Abstract

Provided is a method for manufacturing a semiconductor device. An insulation layer is formed on a bottom structure of a semiconductor substrate. Then, a trench and a via hole are formed by selectively etching the insulation layer, and a copper layer is deposited to fill the via hole and the trench. Next, a copper line is formed by a CMP (chemical mechanical polishing) process to planarize the copper layer, and a plasma process is performed to form a plasma-treated surface layer of the semiconductor substrate. The plasma-treated surface layer is then removed.

Claims

1. A method for manufacturing a semiconductor device, the method comprising:

forming an insulation layer on a bottom structure of a semiconductor substrate;

forming a trench and a via hole by selectively etching the insulation layer;

forming a copper layer on an entire surface of the semiconductor substrate until filling the via hole and the trench;

planarizing the copper layer by chemical mechanical polishing to form a copper line filling the via hole and the trench;

performing a plasma process to form a plasma-treated surface layer on the semiconductor substrate; and

removing the plasma-treated surface layer, wherein removing the surface layer of the Semiconductor substrate comprises;

performing a radio frequency pre-clean process using an Ar plasma, and a Ge ion implantation process.

2. The method according to claim 1, wherein performing the plasma process comprises generating H⁺ in a remote plasma and reacting the H⁺ with the surface of the semiconductor substrate.

3. The method according to claim 2, wherein generating the H⁺ comprises ionizing SiH₄ gas with an Ar remote plasma.

4. The method according to claim 3, wherein ionizing the SiH₄ gas with the Ar remote plasma is performed at a voltage of 100 to 1000 eV for a length of time of 1 to 2 min.

5. The method according to claim 2, wherein generating the H⁺ comprises ionizing NH₃ gas with an Ar remote plasma.

6. The method according to claim 5, wherein ionizing the NH₃ gas with the Ar remote plasma is performed at a voltage of 100 to 1000 eV for a length of time of 1 to 2 min.

7. The method according to claim 1, wherein generating the Ge ion implantation process comprises flowing a Ge-containing gas into an Ar plasma at a voltage of 1000 to 4000 eV for a length of time of 1 to 2 min.

8. A method for manufacturing a semiconductor device, the method comprising:

forming an insulation layer on a bottom structure of a semiconductor substrate;

forming a trench and a via hole by selectively etching the insulation layer;

forming a copper layer on an entire surface of the semiconductor substrate until filling the via hole and the trench;

planarizing the copper layer by chemical mechanical polishing to form a copper line filling the via hole and the trench;

performing a plasma process to form a plasma-treated surface layer on the semiconductor substrate; and

removing the plasma-treated surface layer, wherein removing the surface layer of the semiconductor substrate comprises a Ge ion implantation process.

9. A method for a semiconductor device, the method comprising:

forming an insulation layer on a bottom structure of a semiconductor substrate;

forming a trench and a via hole by selectively etching the insulation layer;

forming a copper layer on an entire surface of the semiconductor substrate until filling the via hole and the trench;

planarizing the copper layer by a chemical mechanical polishing process to form a copper line filling the via hole and the trench;

amorphizing a surface layer of the semiconductor substrate having the copper line thereon;

performing a plasma process to form a plasma-treated, amorphous surface layer; and

removing the plasma-treated, amorphous surface layer.

10. The method according to claim 9, wherein amorphizing the surface layer of the semiconductor substrate comprises implanting Ge ions.

11. The method according to claim 9, wherein performing the plasma process comprises generating H⁺ and/or H. in a remote plasma and reacting H⁺ and/or H. with the surface of the semiconductor substrate having the copper line thereon.

12. The method according to claim 11, wherein generating the H⁺ and/or H. comprises ionizing SiH₄ gas with an Ar remote plasma.

13. The method according to claim 12, wherein the SiH₄ gas is ionized with the Ar remote plasma at a voltage of 100 to 1000 eV for a period of time of 1 to 2 min.

14. The method according to claim 11, wherein generating the H⁺ and/or H. comprises ionizing NH₃ gas with an Ar remote plasma.

15. The method according to claim 9, wherein removing the surface layer of the semiconductor substrate comprises performing a radio frequency pre-clean process using an Ar plasma.

16. The method according to claim 15, wherein removing the surface layer of the semiconductor substrate further comprises a Ge ion implantation process.

17. The method according to claim 16, wherein the Ge ion implantation process comprises flowing a Ge-containing gas into an Ar plasma at a voltage of 1000 to 4000 eV for a length of time of 1 to 2 min.

18. The method according to claim 9, wherein removing the surface layer of the semiconductor substrate comprises a Ge ion implantation process.