Vertical Fin-FET MOS devices
First Claim
Patent Images
1. A vertical Fin-FET semiconductor device characterized by:
- At least one vertical semiconductor fin (12A) disposed on an insulator layer (4);
Doped source (26A) and drain regions (28A) in bottom and top portions of the at least one semiconductor fin (12A); and
Gate conductors (24A, 24B) disposed along vertical sidewalls of the at least one semiconductor fin (12A) and separated therefrom by thin gate insulators (22);
Source conductors (18A, 18B) contacting the source region (26A) on opposite sides of the at least one semiconductor fin (12A);
At least one source contract (38A) connecting to at least one source conductor (18A, 18B);
At least one drain contact (40A) connecting to the drain region (28A) of the at least one semiconductor fin (12A);
A vertical channel region in the fin (12A) between the source region (26A) and the drain region (28A); and
At least one gate contact (42A) connection to at least one gate conductor (24A, 24B).
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Abstract
A new class of high-density, vertical Fin-FET devices that exhibit low contact resistance is described. These vertical Fin-FET devices have vertical silicon “fins” (12A) that act as the transistor body. Doped source and drain regions (26A, 28A) are formed at the bottoms and tops, respectively, of the fins (12A). Gates (24A, 24B) are formed along sidewalls of the fins. Current flows vertically through the fins (12A) between the source and drain regions (26A, 28A) when an appropriate bias is applied to the gates (24A, 24B). An integrated process for forming pFET, nFET, multi-fin, single-fin, multi-gate and double-gate vertical Fin-FETs simultaneously is described.
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Citations
21 Claims
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1. A vertical Fin-FET semiconductor device characterized by:
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At least one vertical semiconductor fin (12A) disposed on an insulator layer (4); Doped source (26A) and drain regions (28A) in bottom and top portions of the at least one semiconductor fin (12A); and Gate conductors (24A, 24B) disposed along vertical sidewalls of the at least one semiconductor fin (12A) and separated therefrom by thin gate insulators (22); Source conductors (18A, 18B) contacting the source region (26A) on opposite sides of the at least one semiconductor fin (12A); At least one source contract (38A) connecting to at least one source conductor (18A, 18B); At least one drain contact (40A) connecting to the drain region (28A) of the at least one semiconductor fin (12A); A vertical channel region in the fin (12A) between the source region (26A) and the drain region (28A); and At least one gate contact (42A) connection to at least one gate conductor (24A, 24B). - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15)
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14. A vertical Fin-FET device characterized by:
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a thin vertical silicon fin (12A) formed in a silicon layer (6) of an SOI substrate; doped source and drain regions (26A, 28A) formed in bottom and top portions, respectively, of the fin; a pair of gate conductors (24A, 24B) disposed along opposite vertical sidewalls of the fin (12A), separated from the fin by thin gate insulators (22) and spanning a vertical distance between the source and drain regions (26A, 26B); a pair of source conductors (18A, 18B) disposed alongside of and in contact with the source region (26A) on opposite sides of the fin (12A); a drain contact (40A) connecting to the drain region (28A); a source contact (38A) connecting to the source conductors (18A, 18B); and at least one gate contact (42A) connecting to at least one gate conductor (24A). - View Dependent Claims (16, 17, 18)
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19. A method of forming a vertical Fin-FET device, characterized by the steps of:
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providing a semiconductor substrate having a semiconductor layer (6) disposed over an insulator layer (4); forming vertical semiconductor fins (12A) on top of the insulator layer (4) by etching parallel trenches (10A, 10B) through the semiconductor layer down to the insulator layer (4); selectively depositing doped conductors (18A, 18B) at the bottoms of the trenches (10A, 10B) such that the doped source conductors contact bottom portions of the fins; forming source insulators (20A, 20B) over the doped conductors (18A, 18B); forming gate insulators (22) along sidewalls of the trenches; thermally driving dopants from the doped conductors into bottom portions of the fins (12A) to form source regions (26A) in the fins (12A); forming gate conductors (24A, 24B) along vertical sidewalls of the fins (12A), spaced away therefrom by the gate insulators (22); doping top portions of the fins (12A) to form drain regions (28A) therein; forming sidewall spacers (30) along exposed sidewalls of the trenches (10A, 10B), fins (12A) and gate conductors (24A, 24B); etching back the source insulators to expose the underlying doped source conductors; forming silicide in exposed portions of the source and gate conductors; filling the trenches with an oxide trench-fill and planarizing; and forming metal source, drain and gate contacts by Damascene processes of selective etching, metal fill, and chem-mech polishing. - View Dependent Claims (20, 21)
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Specification