Level shifter having single voltage source

• US 7,683,667 B2
• Filed: 10/09/2007
• Issued: 03/23/2010
• Est. Priority Date: 10/26/2006
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Dongbu HiTek Co., Ltd.
• Inventors: Kim, Min Hwahn
• Primary Examiner(s): JEANGLAUDE, JEAN BRUNER
• Application Number:
  US11/869,408
• Publication Number:
  US 20080100341A1
• Time in Patent Office: 896 Days
• Field of Search: 326/88, 326/63, 326/112, 326/119, 326/121, 326/86, 326/17, 327/333
• US Class Current: 326/63
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

Embodiments relate to a level shifter which uses a single voltage source, has an excellent operation characteristic even when a difference between a low voltage and a high voltage is large, and can be easily designed. Embodiments relate to a level shifter for shifting a voltage level between an input terminal connected to a circuit block which operates by a low voltage source and an output terminal connected to a circuit block which operates by a high voltage source. In embodiments, the level shifter may include a pull-up PMOS and a pull-down NMOS, both of which are connected between the high voltage source and ground in the form of an inverter and have an output node connected to the output terminal. The level shifter may include a control node which is connected to inputs of the pull-up and pull-down NMOS in the form of the inverter. The level shifter may have an input gate for connecting the control node to the high voltage source or ground according to a voltage level of the input terminal. The level shifter may also include a first feedback chain which is connected between the control node and the input gate and disconnects the input gate and the high voltage source when the voltage level of the input terminal is high and the input gate connects the control node to ground.

Claims

1. An apparatus comprising:

a pull-up PMOS transistor and a pull-down NMOS transistor connected in series between a high voltage source and ground as an inverter, and having an output node connected to an output terminal;

a control node which is connected to inputs of the pull-up PMOS transistor and pull-down NMOS transistor;

an input gate for connecting the control node to the high voltage source or ground according to a voltage level of the input terminal; and

a first feedback chain which is connected between the control node and the input gate such that when the voltage level of the input terminal is high, the feedback chain disconnects a path from the high voltage source to the control node via the input gate, while the input gate connects the control node to ground.

2. The apparatus of claim 1, comprising a second feedback chain which is connected between the output terminal and the control node and connects the control node to the high voltage source when the voltage level of the input terminal is low and the input gate connects the control node to the high voltage source.

3. The apparatus of claim 2, wherein the input gate comprises:

a first PMOS transistor with a gate connected to the input terminal, a source connected to the high voltage source, and a drain connected to the control node via the first feedback chain; and

a first NMOS transistor with a gate connected to the input terminal, a source connected to ground, and a drain connected to the control node.

4. The apparatus of claim 3, wherein:

the first feedback chain comprises a second PMOS transistor with a gate connected to the control node and a drain connected to ground and a second NMOS transistor with a source connected to the control node and a drain connected to the drain of the first PMOS transistor, and

the source of the second PMOS transistor is connected to the gate of the second NMOS transistor.

5. The apparatus of claim 2, wherein the second feedback chain comprises a fourth PMOS transistor with a gate is connected to the output terminal, a source connected to the high voltage source, and a drain connected to the control node.

6. The apparatus of claim 2, wherein the input gate comprises:

a 2-1th PMOS transistor with a gate is connected to the input terminal, a source connected to the high voltage source, and a drain connected to the control node via the first feedback chain, and a 2-2th PMOS transistor with a gate connected to an enable terminal, a source connected to the high voltage source, and a drain connected to the control node via the first feedback chain; and

a 2-1th NMOS transistor with a gate connected to the input terminal and a source connected to ground, and a 2-2th NMOS transistor with a gate connected to the enable terminal, a source connected to a drain of the 2-1th NMOS transistor, and a drain connected to the control node.

7. The apparatus of claim 6, wherein:

the first feedback chain comprises a second PMOS transistor with a gate connected to the control node and a drain connected to ground and a second NMOS transistor with a source connected to the control node and a drain connected to the drain of the first PMOS transistor, and

a source of the second PMOS transistor is connected to a gate of the second NMOS transistor.

8. The apparatus of claim 1, wherein the first feedback chain comprises an NMOS transistor with a source connected to ground, a gate connected to the output terminal, and a drain connected to the gate of the input inverter.

9. The apparatus of claim 1, wherein the input gate comprises:

a first PMOS transistor with a gate connected to the input terminal, a source connected to the high voltage source, and a drain connected to the control node via the first feedback chain; and

a first NMOS transistor with a gate connected to the input terminal, a source connected to ground, and a drain connected to the control node.

10. The apparatus of claim 9, wherein:

the first feedback chain comprises a second PMOS transistor with a gate connected to the control node and a drain connected to ground and a second NMOS transistor with a source connected to the control node and a drain connected to the drain of the first PMOS transistor, and

the source of the second PMOS transistor is connected to the gate of the second NMOS transistor.

11. The apparatus of claim 1, wherein the input gate comprises:

a 2-1th PMOS transistor with a gate is connected to the input terminal, a source connected to the high voltage source, and a drain connected to the control node via the first feedback chain, and a 2-2th PMOS transistor with a gate connected to an enable terminal, a source connected to the high voltage source, and a drain connected to the control node via the first feedback chain; and

a 2-1th NMOS transistor with a gate connected to the input terminal and a source connected to ground, and a 2-2th NMOS transistor with a gate connected to the enable terminal, a source connected to a drain of the 2-1th NMOS transistor, and a drain connected to the control node.

12. The apparatus of claim 11, wherein:

the first feedback chain comprises a second PMOS transistor with a gate connected to the control node and a drain connected to ground and a second NMOS transistor with a source connected to the control node and a drain connected to the drain of the first PMOS transistor, and

a source of the second PMOS transistor is connected to a gate of the second NMOS transistor.

13. A method comprising:

manufacturing a level shifter for shifting a voltage level between an input terminal connected to a circuit block which operates by a low voltage source and an output terminal connected to a circuit block which operates by a high voltage source, by;

selecting a specification of a level shifter;

selecting an implant condition of a MOS transistor forming the transistor;

determining whether a preselected condition is matched;

using the implant condition to form a cell of the level shifter if the preselected condition is matched; and

selecting a different specification of a level shifter if the preselected condition is not matched.

14. The method of claim 13, wherein the preselected condition is relatively high speed operation.

15. The method of claim 14, wherein the implant condition is selected for a relatively low threshold voltage MOS transistor.

16. The method of claim 13, wherein the preselected condition is relatively low power operation.

17. The method of claim 16, wherein the implant condition is selected for a relatively high threshold voltage MOS transistor.

18. The method of claim 13, wherein the preselected condition is relatively low leakage current operation.

19. The method of claim 18, wherein the implant condition is selected for an intermediate threshold voltage MOS transistor.

20. The method of claim 13, wherein a level shifter is formed as a cellular unit, and a library of cells may be combined in a circuit containing a plurality of circuit blocks requiring voltage level shifting for device interoperation.