High performance, area efficient direct bitline sensing circuit

• US 7,684,274 B2
• Filed: 12/10/2007
• Issued: 03/23/2010
• Est. Priority Date: 12/10/2007
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Rengarajan, Santhana, Balasubramanian, Suresh
• Primary Examiner(s): Lam; David
• Application Number:
  US11/953,075
• Publication Number:
  US 20090147605A1
• Time in Patent Office: 834 Days
• Field of Search: 365/207, 365/205, 365/154, 365/203, 365/189.15, 365/189.05
• US Class Current: 365/207
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs

Abstract

In a method and apparatus for reading a logic state stored in an 8 transistor memory cell (8TMC), a differential sense circuit includes a differential input circuit having a pair of differential inputs and an output. An output signal is provided at the output and is indicative of a difference between two signals received at the pair of differential inputs. The difference is in accordance with the logic state read from the 8TMC. A sense amplifier is coupled to the output, the sense amplifier being operable to amplify the output signal that is greater than a threshold and switch the output signal to a voltage level corresponding to the logic state. The difference between the two signals measurable over a configurable time period is greater than a corresponding change in any one of the two signals measured over the same period, thereby improving the performance of the 8TMC.

Claims

1. A differential sense circuit for reading an 8 transistor (8T) memory cell, the differential sense circuit comprising:

a differential input circuit having a pair of differential inputs and an output, wherein an output signal provided at the output is indicative of a difference between two signals received at the pair of differential inputs, wherein the difference is in accordance with a logic state read from the 8T memory cell; and

a sense amplifier coupled to the output, wherein the sense amplifier is operable to amplify a change in the output signal, the change being greater than a threshold, wherein the sense amplifier switches the output signal to have a voltage level corresponding to the logic state,

wherein a first one of the pair of differential inputs is coupled to a soft ground level reference node of a read buffer of the 8T memory cell and a second one of the pair of differential inputs is coupled to a read bit line of the read buffer.

2. The differential sense circuit of claim 1, wherein a voltage level at the soft ground level reference node is controllable by a switch disposed between the soft ground level reference node and a ground level bias supply voltage provided to the 8T memory cell.

3. The differential sense circuit of claim 1, wherein the change in the output signal being less than the threshold is indicative of a low logic state read from the 8T memory cell, and the difference being greater than the threshold is indicative of a high logic state read from the 8T memory cell.

4. The differential sense circuit of claim 1, wherein the sense amplifier is shared between a plurality of columns of an array formed by multiple ones of the 8T memory cell.

5. The differential sense circuit of claim 1, wherein the differential input circuit includes:

a pull-up circuit shared between a plurality of columns of an array formed by multiple ones of the 8T memory cell, wherein the pull-up circuit is operable to couple the output to a logic high level during an initialization phase; and

a pull-down circuit coupled to receive the pair of differential inputs and provide the output signal at the output, wherein the pull-down circuit includes;

a column select switch coupled to the output, wherein the column select switch corresponds to each one of the plurality of columns;

a first input switch coupled to the column select switch, the first input switch having a first gate coupled to a first one of the pair of differential inputs, the first gate being coupled to a soft ground level reference node of a read buffer of the 8T memory cell;

a second input switch having a second gate coupled to a second one of the pair of differential inputs, the second gate being coupled to a read bit line of the 8T memory cell;

a gate switch having a gate coupled to the second input switch, the gate switch being operable to couple the second input switch and the column select switch;

an initialization circuit having a first initialization switch and a second initialization switch, wherein the first initialization switch is operable to equalize voltages at the soft ground level reference node, the gate of the gate switch, and a ground level bias supply provided to the 8T memory cell during the initialization phase.

6. The differential sense circuit of claim 5, wherein the read bit line is precharged to the logic high level during the initialization phase.

7. The differential sense circuit of claim 1, wherein the sense amplifier includes:

a pair of cross-coupled inverters forming two nodes, wherein a first one of the two nodes is coupled to the output, wherein the pair of cross-coupled inverters are operable to amplify the output signal to one of a high logic state and a low logic state in accordance with the difference, the difference being greater than the threshold; and

a sense enable switch operable to enable the pair of cross-coupled inverters to amplify the output signal in accordance with the difference.

8. The differential sense circuit of claim 7, wherein the pair of cross-coupled inverters includes a deliberate offset circuit to force a second one of the two nodes to have a voltage offset relative to the first one, wherein the voltage offset causes the pair of cross-coupled inverters to store the logic state read from the 8T memory cell in accordance with the difference, the difference being less than the threshold.

9. The differential sense circuit of claim 7, wherein the two nodes are precharged to a logic high level before the sense enable switch is enabled.

10. The differential sense circuit of claim 1 further comprising:

an offset assist circuit coupled to the differential input circuit, wherein the offset assist circuit is operable to accelerate the change in a voltage level of the output signal in response to the change being greater than the threshold.

11. The differential sense circuit of claim 1, wherein the difference between the two signals measured over a configurable time period is greater than a corresponding change in any one of the two signals measured over the configurable time period.

12. The differential sense circuit of claim 11, wherein a faster change in the difference provides an improvement in a response time to read the logic state of the 8T memory cell compared to a traditional 8T memory cell.

13. A method for reading a logic state stored in an 8 transistor (8T) memory cell, the method comprising:

coupling a soft ground level reference node of a read buffer of the 8T memory cell to one of two differential inputs of a differential sense amplifier, wherein a second one of the two differential inputs is coupled to a read bit line of the read buffer; and

detecting a differential voltage across the two differential inputs to read the logic state, wherein a change in the differential voltage is indicative of the logic state.

14. The method of claim 13, wherein the read buffer includes a source of a first read switch coupled in series to a drain of a second read switch, wherein a gate of the first read switch is controlled by a storage node of the 8T memory cell, wherein the logic state is stored in the storage node, wherein a gate of the second read switch is controlled by a write line, wherein a source of the second read switch is coupled to the ground level reference node, wherein a drain of the first read switch is coupled to the read bit line.

15. The method of claim 13 further comprising:

precharging the read bit line;

equalizing voltages of the soft ground level reference node and a ground level bias supply provided to the 8T memory cell prior to the detecting; and

asserting the read bit line and a word line of the 8T memory cell to enable the reading.

16. The method of claim 13, wherein the change in the differential voltage is faster compared to a change for any one of the two differential inputs.

17. The method of claim 16, wherein the faster change in the differential voltage provides an improvement in a response time to read the logic state.

18. A memory device comprising:

an array formed by a plurality of rows and a plurality of columns of an 8 transistor (8T) memory cell;

a differential input circuit having a pair of differential inputs and an output, wherein an output signal provided at the output is a difference between two signals received at the pair of differential inputs, wherein the difference is indicative of a logic state read from the 8T memory cell, wherein the differential input circuit includes;

a pull-up circuit shared between selected ones of the plurality of columns of the array, wherein the pull-up circuit is operable to couple the output to a logic high level during an initialization phase;

a pull-down circuit corresponding to each of the selected ones of the plurality of columns, wherein the pull-down circuit is coupled to receive the pair of differential inputs and provide the output signal at the output; and

a sense amplifier coupled to the output, wherein the sense amplifier is shared between the selected ones of the plurality of columns of the array, wherein the sense amplifier is operable to amplify the output signal to the logic state in response to the difference being greater than a threshold.

19. The memory device of claim 18, wherein the selected ones of the plurality of columns is at most equal to 4.