Radio receiver, system on a chip integrated circuit and methods for use therewith

• US 7,684,515 B2
• Filed: 11/22/2005
• Issued: 03/23/2010
• Est. Priority Date: 11/22/2005
• Status: Expired due to Fees

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: SigmaTel Incorporated (NXP Semiconductors NV)
• Inventors: May, Michael R., Lowe, Erich
• Primary Examiner(s): Wang, Ted M
• Application Number:
  US11/287,551
• Publication Number:
  US 20070116147A1
• Time in Patent Office: 1,582 Days
• Field of Search: 375/316, 375/147, 375/324, 375/326, 375/340
• US Class Current: 375/316
• CPC Class Codes: H04B 15/02 Reducing interference from electric apparatus by means located at or near the interfering apparatus
• CPC Class Codes: H04B 2215/064 Reduction of clock or synthesizer reference frequency harmonics

Abstract

A system on a chip integrated circuit includes a first digital module and a second digital module such that the second digital module generates an output during the predetermined period that is based on an output of the first digital module generated during a prior predetermined period. A digital clock generator generates a base clock signal having a plurality of first digital clock cycles over a predetermined period and a second digital clock signal having a plurality of second digital clock cycles over the predetermined period. The plurality of first digital clock cycles are substantially interleaved with the plurality of second digital clock cycles over the predetermined period.

Claims

1. A radio receiver comprising:

an analog front end for receiving a received radio signal containing a selected one of the plurality of channel signals, and for converting the selected one of the plurality of channel signals into a digital signal;

a digital section, operably coupled to the analog front end and a digital clock generator, for converting the digital signal into at least one audio signal that corresponds to the selected one of the plurality of channels, the digital section having a first digital module and a second digital module; and

the digital clock generator, operably coupled to the first digital module and the second digital module, for generating a base clock signal having a plurality of first digital clock cycles over a predetermined period and a second digital clock signal having a plurality of second digital clock cycles over the predetermined period, wherein the plurality of first digital clock cycles are substantially interleaved with the plurality of second digital clock cycles over the predetermined period;

wherein the second digital module generates an output during the predetermined period that is based on an output of the first digital module generated during a prior predetermined period; and

wherein the plurality of first digital clock cycles are not equal to the plurality of second digital clock cycles over the predetermined period.

2. The radio receiver of claim 1 wherein the plurality of first digital clock cycles are two or more times greater than the plurality of second digital clock cycles over the predetermined period.

3. The radio receiver of claim 1 wherein the digital clock generator generates the base clock signal at a base clock frequency that varies based on the selected one of the plurality of channel signals and wherein the plurality of first digital clock cycles and the plurality of second digital clock cycles are substantially constant over the predetermined period.

4. The radio receiver of claim 3 wherein the base clock frequency is less than a carrier frequency of the selected one of the plurality of channel signals and wherein the base clock frequency, and integer multiples of the base clock frequency are not substantially equal to the carrier frequency of the selected one of the plurality of channel signals.

5. The radio receiver of claim 1 wherein the predetermined period is one of:

a sample period, a decimation period, and a computational period.

6. The radio receiver of claim 1 wherein the digital clock generator alternates between generating one or more of the plurality of first digital clock cycles with one or more of the plurality of second digital clock cycles over the predetermined period.

7. The radio receiver of claim 1 wherein the digital clock generator generates at least one of the plurality of first digital clock cycles in synchronism with at least one of the plurality of second digital clock cycles over the predetermined period.

8. The radio receiver of claim 1 wherein the received radio signal is one of:

a broadcast frequency modulated radio signal, a broadcast amplitude modulated radio signal, a broadcast satellite radio signal, and a broadcast cable signal.

9. The radio receiver of claim 1 wherein at least one of:

the analog front end, the digital clock generator, and the digital section, are implemented as part of a system on a chip integrated circuit.

10. An integrated circuit (IC) comprising:

a first digital module;

a second digital module; and

a digital clock generator, operably coupled to the first digital module and the second digital module, for generating a base clock signal having a plurality of first digital clock cycles over a predetermined period and a second digital clock signal having a plurality of second digital clock cycles over the predetermined period, wherein the plurality of first digital clock cycles are substantially interleaved with the plurality of second digital clock cycles over the predetermined period;

wherein the second digital module generates an output during the predetermined period that is based on an output of the first digital module generated during a prior predetermined period; and

wherein the plurality of first digital clock cycles are not equal to the plurality of second digital clock cycles over the predetermined period.

11. The integrated circuit (IC) of claim 10 wherein the digital clock generator generates the base clock signal at a base clock frequency that varies based on a control signal and wherein the plurality of first digital clock cycles and the plurality of second digital clock cycles are constant over the predetermined period.

12. The integrated circuit (IC) of claim 10 wherein the digital clock generator alternates between generating one or more of the plurality of first digital clock cycles with one or more of the plurality of second digital clock cycles over the predetermined period.

13. The integrated circuit (IC) of claim 10 wherein the digital clock generator generates at least one of the plurality of first digital clock cycles in synchronism with at least one of the plurality of second digital clock cycles over the predetermined period.

14. The radio received of claim 10 wherein the predetermined period is one of:

a sample period, a decimation period, and a computational period.

15. A method comprising:

generating, at a digital clock generator, a base clock signal having a plurality of first digital clock cycles over a predetermined period to clock a first digital submodule; and

generating, at the digital clock generator, a second digital clock signal having a plurality of second digital clock cycles over the predetermined period to clock a second digital submodule,

wherein the plurality of first digital clock cycles are substantially interleaved with the plurality of second digital clock cycles over the predetermined period, and wherein the second digital module generates an output during the predetermined period that is based on an output of the first digital module generated during a prior predetermined period; and

wherein the plurality of first digital clock cycles are not equal to the plurality of second digital clock cycles over the predetermined period.

16. The method of claim 15 wherein:

generating the base clock signal includes generating the base clock signal at a base clock frequency that varies based on a control signal;

wherein the plurality of first digital clock cycles and the plurality of second digital clock cycles are constant over the predetermined period.

17. The method of claim 15 wherein the plurality of first digital clock cycles alternate with one or more of the plurality of second digital clock cycles over the predetermined period.

18. The method of claim 15 wherein at least one of the plurality of first digital clock cycles is generated in synchronism with at least one of the plurality of second digital clock cycles over the predetermined period.