Generation of a high-level simulation model of an electronic system by combining an HDL control function translated to a high-level language and a separate high-level data path function

• US 7,684,968 B1
• Filed: 12/09/2004
• Issued: 03/23/2010
• Est. Priority Date: 12/09/2004
• Status: Expired due to Fees

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Hwang, L. James, Szedo, Gabor, Jitendra, Singh Vinay
• Primary Examiner(s): Vincent; David R
• Assistant Examiner(s): Rifkin; Ben M
• Application Number:
  US11/010,027
• Time in Patent Office: 1,930 Days
• Field of Search: 703/14, 717/104, 717/137, 716/3, 716/18
• US Class Current: 703/14
• CPC Class Codes: G06F 2117/08 HW-SW co-design, e.g. HW-SW partitioning
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

Generating a high-level, bit-accurate and cycle-accurate simulation model. The various embodiments generate the simulation model from a functional description of a module and an HDL description of the module. The functional description may be un-timed and specified in a high-level language. The HDL description is realizable in hardware. The simulation model is created by obtaining the control specification from the HDL description and combining the control specification with the data path description from functional description.

Claims

1. A processor-implemented method for generating a hybrid simulation model for a design block in an electronic system, comprising:

reading a first high-level modeling language description of a data path function, wherein the first high-level modeling language description of the data path function is without a control function that provides a cycle-accurate simulation of the data path function;

reading a hardware description language (HDL) specification of the design block, wherein the HDL specification of the design block includes an HDL description of the control function and an HDL description of the data path function;

converting the HDL specification of the design block to a high-level modeling language description of the design block, wherein the high-level modeling language description of the design block includes a second high-level modeling language description of the data path function and a high-level modeling language description of the control function;

determining the high-level modeling language description of the control function from the high-level modeling language description of the design block, wherein the description of the control function specifies cycle-accurate behavior of the design block without reference to functions in the design block that transform data; and

combining the high-level modeling language description of the control function in the high-level modeling language with the first high-level modeling language description of the data path function into a bit-true and cycle-accurate hybrid simulation model in the high-level modeling language, wherein the first high-level modeling language description of the data path function is a bit-true specification of functions of the design block that transform data.

2. The method of claim 1, further comprising:

compiling the hybrid simulation model in the high-level modeling language into at least one object file; and

wherein the step of combining includes linking the at least one object file to at least one other object file that is a simulation model of another design block.

3. The method of claim 2, wherein the linking step is performed at initialization of simulation execution using dynamically linked libraries.

4. The method of claim 1, wherein the determining the description of the control function from the high-level modeling language description includes searching for tags in the high-level modeling language description indicative of the control function.

5. The method of claim 4, further comprising:

identifying input signals and output signals in the first high-level modeling language data path description;

removing the identified input and output signals from the high-level modeling language description of the design block; and

removing unconnected functions from the high-level modeling language description of the design block.

6. The method of claim 1, further comprising generating one or more interface programs from the HDL specification of the design block, each interface program configured to convert a data format for one of input to and output from the design block during simulation.

7. The method of claim 1, wherein the high-level modeling language is C++.

8. The method of claim 1, wherein the high-level modeling language is C.

9. The method of claim 1, wherein the high-level modeling language is MATLAB.

10. The method of claim 1, wherein the high-level modeling language is Simulink.

11. The method of claim 1, wherein the high-level modeling language is Javascript.

12. The method of claim 1, wherein the HDL is VHDL.

13. The method of claim 1, wherein the HDL is Verilog.

14. An apparatus for generating a hybrid simulation model for a design block in an electronic system, comprising:

means for reading a first high-level modeling language description of a data path function, wherein the first high-level modeling language description of the data path function is without a control function that provides a cycle-accurate simulation of the data path function;

means for reading a hardware description language (HDL) specification of the design block, wherein the HDL specification of the design block includes an HDL description of the control function and an HDL description of the data path function;

means for converting the HDL specification of the design block to a high-level modeling language description of the design block, wherein the high-level modeling language description of the design block includes a second high-level modeling language description of the data path function and a high-level modeling language description of the control function;

means for determining the high-level modeling language description of the control function from the high-level modeling language description of the design block, wherein the description of the control function specifies cycle-accurate behavior of the design block without reference to functions in the design block that transform data;

means for combining the high-level modeling language description of the control function in the high-level modeling language with the first high-level modeling language description of the data path function into a bit-true and cycle-accurate hybrid simulation model in the high-level modeling language, wherein the first high-level modeling language description of the data path function is a bit-true specification of functions of the design block that transform data.