Memory system topologies including a buffer device and an integrated circuit memory device

• US 7,685,364 B2
• Filed: 04/15/2009
• Issued: 03/23/2010
• Est. Priority Date: 09/26/2005
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Shaeffer, Ian, Tsern, Ely, Hampel, Craig
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US12/424,442
• Publication Number:
  US 20090198924A1
• Time in Patent Office: 342 Days
• Field of Search: 711/115, 711/167, 361/728, 365/53, 365/189.01
• US Class Current: 711/115
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/1005 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

Claims

1. A system comprising:

an integrated circuit buffer device including;

a first interface to receive control information;

a second interface to output the control information and receive data; and

a register to store a value that indicates a number of integrated circuit memory devices to perform a memory access in response to the control information, wherein each memory device included in the number of integrated circuit memory devices, indicated by the value, provides a portion of the data from a corresponding memory access;

a first integrated circuit memory device to output a first portion of the data;

a first signal path coupled to the integrated circuit buffer device and the first integrated circuit memory device, the first signal path to convey the first portion of the data from the first integrated circuit memory device to the integrated circuit buffer device;

a second integrated circuit memory device to output a second portion of the data;

a second signal path coupled to the integrated circuit buffer device and the second integrated circuit memory device, the second signal path to convey the second portion of data from the second integrated circuit memory device to the integrated circuit buffer device; and

a third signal path coupled to the integrated circuit buffer device and the first and second integrated circuit memory devices, the third signal path to convey the control information from the integrated circuit buffer device to both the first and second integrated circuit memory devices.

2. The system of claim 1 wherein the control information received at the first interface of the integrated circuit buffer device includes information from an address field, wherein the control information output at the second interface includes a plurality of chip select signals to select the first and second integrated circuit memory devices in response to at least the information from the address field.

3. The system of claim 1 wherein the control information received at the first interface of the integrated circuit buffer device indicates a read operation and a first page length, wherein the control information output at the second interface specifies a read operation of the first and second integrated circuit memory devices using a second page length, wherein the second page length is different than the first page length.

4. The system of claim 1 wherein the integrated circuit buffer device further comprising:

a third interface; and

a data path router circuit to merge the first and second portions of the first data received from the first and second integrated circuit memory devices, the data path router circuit to provide merged data to the third interface.

5. The system of claim 1 wherein the control information received at the first interface of the integrated circuit buffer device includes a first address,

wherein the integrated circuit buffer device outputs a second address to a memory location of the first integrated circuit memory device as the control information in response to the first address, and

wherein the integrated circuit buffer device outputs a third address to a memory location of the second integrated circuit memory device as the control information in response to the first address.

6. The system of claim 1 wherein the integrated circuit buffer device, the first integrated circuit memory device, the second integrated circuit memory device, the first signal path, the second signal path and the third signal path are included on a memory module.

7. The system of claim 1 wherein the integrated circuit buffer device, the first integrated circuit memory device and the second integrated circuit memory device are dies included in a single package housing.

8. The system of claim 1 wherein:

the integrated circuit buffer device is disposed in a first package housing;

the first integrated circuit memory device is disposed in a second package housing; and

the second integrated circuit memory device is disposed in a third package housing,

wherein the second package housing is stacked on top of the first package housing, and the third package housing is stacked on top of the second package housing.

9. The system of claim 1 wherein:

the first signal path is a first point to point link coupled between the integrated circuit buffer device and the first integrated circuit memory device;

the second signal path is a second point to point link coupled between the integrated circuit buffer device and the second integrated circuit memory device; and

the third signal path is a bus coupled to the integrated circuit buffer device and the first and second integrated circuit memory devices.

10. A system comprising:

a first integrated circuit memory device and a second integrated circuit memory device;

an integrated circuit buffer device including;

a first interface to receive control information;

a second interface to output the control information and receive first data; and

registers to store information indicating a number of signal paths, a number of signal lines included in each signal path of the number of signal paths coupled between the integrated circuit buffer device and each of the first and second integrated circuit memory devices;

a first signal path coupled to the integrated circuit buffer device and the first integrated circuit memory device, the first signal path to convey a first portion of the first data from the first integrated circuit memory device to the integrated circuit buffer device;

a second signal path coupled to the integrated circuit buffer device and the second integrated circuit memory device, the second signal path to convey a second portion first data from the second integrated circuit memory device to the integrated circuit buffer device; and

a third signal path coupled to the integrated circuit buffer device and the first and second integrated circuit memory devices, the third signal path to convey the control information from the integrated circuit buffer device to both the first and second integrated circuit memory devices.

11. The system of claim 10 wherein the control information received at the first interface of the integrated circuit buffer device includes information from an address field, wherein the control information output at the second interface includes a plurality of chip select signals to select the first and second integrated circuit memory devices in response to at least the information from the address field.

12. The system of claim 10 wherein the control information received at the first interface of the integrated circuit buffer device indicates a read operation and a first page length, wherein the control information output at the second interface specifies a read operation of the first and second integrated circuit memory devices using a second page length, wherein the second page length is different than the first page length.

13. The system of claim 10 wherein the integrated circuit buffer device further comprising:

a third interface; and

a data path router circuit to merge the first and second portions of the first data received from the first and second integrated circuit memory devices, the data path router circuit to provide merged data to the third interface.

14. The system of claim 10 wherein the control information received at the first interface of the integrated circuit buffer device includes a first address,

wherein the integrated circuit buffer device outputs a second address to a memory location of the first integrated circuit memory device as the control information in response to the first address, and

wherein the integrated circuit buffer device outputs a third address to a memory location of the second integrated circuit memory device as the control information in response to the first address.

15. The system of claim 10 wherein the integrated circuit buffer device, the first integrated circuit memory device, the second integrated circuit memory device, the first signal path, the second signal path and the third signal path are included on a memory module.

16. The system of claim 10 wherein the integrated circuit buffer device, the first integrated circuit memory device and the second integrated circuit memory device are dies included in a single package housing.

17. The system of claim 10 wherein:

the integrated circuit buffer device is disposed in a first package housing;

the first integrated circuit memory device is disposed in a second package housing; and

the second integrated circuit memory device is disposed in a third package housing,

wherein the second package housing is stacked on top of the first package housing, and the third package housing is stacked on top of the second package housing.

18. The system of claim 10 wherein:

the first signal path is a first point to point link coupled between the integrated circuit buffer device and the first integrated circuit device;

the second signal path is a second point to point link coupled between the integrated circuit buffer device and the second integrated circuit memory device; and

the third signal path is a bus coupled to the integrated circuit buffer device and the first and second integrated circuit memory devices.

19. An integrated circuit buffer device including:

a first interface to receive control information;

a second interface to output the control information and transfer first data associated with the control information; and

a register to store a value that indicates a number of integrated circuit memory devices to perform a memory access in response to the control information, wherein each memory device included in the number of integrated circuit memory devices, indicated by the value, transfers a portion of the data from a corresponding memory access.

20. The integrated circuit buffer device of claim 19 wherein the control information received at the first interface includes information from an address field, wherein the control information output at the second interface includes a plurality of chip select signals to select a first and second integrated circuit memory devices in the number of integrated circuit memory devices in response to at least the information from the address field.

21. The integrated circuit buffer device of claim 19 wherein the control information received at the first interface indicates a read operation and a first page length, wherein the control information output at the second interface specifies a read operation of a first and second integrated circuit memory devices in the number of integrated circuit memory devices using a second page length, wherein the second page length is different than the first page length.

22. The integrated circuit buffer device of claim 19, further comprising:

a third interface; and

a data path router circuit to merge the portions of the data received from memory accesses corresponding to each memory device included in the number of integrated circuit memory devices, the data path router circuit to provide merged data to the third interface.

23. The integrated circuit buffer device of claim 19 wherein the control information received at the first interface includes a first address,

wherein the integrated circuit buffer device includes an address translation circuit to provide, in response to the first address:

a second address indicating a first memory location in a memory array of a first integrated circuit memory device in the number of integrated circuit memory devices; and

a third address indicating a second memory location in a memory array of a second integrated circuit memory device in the number of integrated circuit memory devices.

24. The integrated circuit buffer device of claim 19, further comprising:

registers to store information indicating a number of signal paths, a number of signal lines included in each signal path of the number of signal paths coupled between the integrated circuit buffer device and each of a first and second integrated circuit memory devices in the number of integrated circuit memory devices.

25. A module comprising:

a first integrated circuit memory device and a second integrated circuit memory device;

an integrated circuit buffer device coupled to the first integrated circuit memory device and the second integrated circuit memory device, the integrated circuit buffer device including;

a first interface to receive control information;

a second interface to output the control information and receive first data; and

registers to store information indicating a number of signal paths, a number of signal lines included in each signal path of the number of signal paths coupled between the integrated circuit buffer device and each of the first and second integrated circuit memory devices.