RISC microprocessor architecture implementing multiple typed register sets

• US 7,685,402 B2
• Filed: 01/09/2007
• Issued: 03/23/2010
• Est. Priority Date: 07/08/1991
• Status: Expired due to Fees

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Inventors: Nguyen, Le Trong, Chen, Sho Long, Garg, Sanjiv, Lentz, Derek J.
• Primary Examiner(s): Donaghue; Larry D
• Application Number:
  US11/651,009
• Publication Number:
  US 20070113047A1
• Time in Patent Office: 1,169 Days
• Field of Search: 712/23, 712/228, 712/212, 712217-219
• US Class Current: 712/23
• CPC Class Codes: G06F 9/30029 Logical and Boolean instructions, e.g. XOR, NOT
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/30116 Shadow registers, e.g. coupled registers, not forming part of the register space
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/30138 Extension of register space, e.g. register cache
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming

Abstract

A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA[23:0]) and second (RA[31:24]) subsets, and a shadow subset (RT[31:24]). While the data processor is in a first mode, instructions access the first and second subsets. While the data processor is in a second mode, instructions may access the first subset, but any attempts to access the second subset are re-routed to the shadow subset instead, transparently to the instructions, allowing system routines to seemingly use the second subset without having to save and restore data which user routines have written to the second subset. A re-typable register set provides integer width data and floating point width data in response to integer instructions and floating point instructions, respectively. Boolean comparison instructions specify particular integer or floating point registers for source data to be compared, and specify a particular Boolean register for the result, so there are no dedicated, fixed-location status flags. Boolean combinational instructions combine specified Boolean registers, for performing complex Boolean comparisons without intervening conditional branch instructions, to minimize pipeline disruption.

Claims

1. An apparatus configured to execute a set of instructions, the instructions including one or more fields, wherein a field of a given instruction specifies a source or an operand of the given instruction or a destination of a result of the given instruction, and wherein the apparatus comprises:

an execution unit configured to execute the instructions; and

a register file, coupled to the execution unit, configured to store operands and results of the instructions, wherein,

the register file includes a plurality of register sets, each of the register sets including;

a first register set having a plurality of registers each of which is configured to store data of a single data type; and

a second register set having a plurality of registers, each of which is configured to store data of a plurality of data types, and

wherein the register file is responsive to one or more of the fields in a given instruction to retrieve an operand of the given instruction from, or store a result of the given instruction into, a given register in a given one of the register sets as identified by the one or more fields of the given instruction.

2. The apparatus of claim 1, wherein:

the first register set comprises a first subset of registers, a second subset of registers, and a shadow set of registers,

the shadow subset of registers has the same number of registers as the number of registers in the second subset of registers, and

in a first operating mode each operand access to the second subset of registers is directed to the second subset of registers, and in a second operating mode each operand access to the second subset of registers is directed to the shadow registers.

3. The apparatus of claim 2, wherein each operand access to the first subset of registers is directed to the first subset of registers.

4. The apparatus of claim 1, wherein each register in the first register set is configured to store an integer value and each register in the second register set is configured to store an integer value or a floating point value.

5. The apparatus of claim 1, wherein one register of the first register set is dedicated to the value zero (0), and one register in the second register set is dedicated to the value zero (0).

6. The apparatus of claim 1, wherein the register sets further comprise a third register set comprising a plurality of registers, each of which is configured to store a Boolean value.

7. A method for executing an instruction in an instruction execution unit, comprising:

decoding the instruction having one or more fields, wherein a field of a given instruction specifies a source or an operand of the given instruction or a destination of a result of the given instruction;

accessing a register file coupled to the instruction execution unit, wherein the register file includes a plurality of register sets to store operands to execute the instruction and a result of executing the instruction, the register sets including;

a first register set having a plurality of registers each of which is configured to store data of a first data type, and

a second register set having a plurality of registers each of which is configured to store data of the first data type or data of a second data type;

retrieving an operand of the given instruction from a given register in a given one of the register sets as identified by decoding the instruction; and

storing a result of the given instruction into a given register in a given one of the register sets as identified by the decoding of the instruction.

8. The method of claim 7, further comprising:

using a first subset of registers, a second subset of registers, and a shadow set of registers as the first register set, wherein the shadow subset of registers has the same number of registers as the number of registers in the second subset of registers;

in a first operating mode, directing each operand access to the second subset of registers to the second subset of registers; and

in a second operating mode, directing each operand access to the second subset of registers to the shadow registers.

9. The method of claim 8, further comprising directing each access to the first subset of registers to the first subset of registers.

10. The method of claim 7, wherein the first data type is integer data and the second data type is floating point data.

11. The method of claim 7, further comprising:

dedicating a register of the first register set to a permanent value of zero (0); and

dedicating a register of the second register set to a permanent value of zero (0).

12. The method of claim 7, further comprising:

including a third register set in the register sets, the third register set comprising a plurality of registers, each of the registers storing a Boolean value.