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RISC microprocessor architecture implementing multiple typed register sets

  • US 7,685,402 B2
  • Filed: 01/09/2007
  • Issued: 03/23/2010
  • Est. Priority Date: 07/08/1991
  • Status: Expired due to Fees
First Claim
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1. An apparatus configured to execute a set of instructions, the instructions including one or more fields, wherein a field of a given instruction specifies a source or an operand of the given instruction or a destination of a result of the given instruction, and wherein the apparatus comprises:

  • an execution unit configured to execute the instructions; and

    a register file, coupled to the execution unit, configured to store operands and results of the instructions, wherein,the register file includes a plurality of register sets, each of the register sets including;

    a first register set having a plurality of registers each of which is configured to store data of a single data type; and

    a second register set having a plurality of registers, each of which is configured to store data of a plurality of data types, andwherein the register file is responsive to one or more of the fields in a given instruction to retrieve an operand of the given instruction from, or store a result of the given instruction into, a given register in a given one of the register sets as identified by the one or more fields of the given instruction.

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