Early notification of error via software interrupt and shared memory write

• US 7,685,476 B2
• Filed: 09/12/2006
• Issued: 03/23/2010
• Est. Priority Date: 09/12/2006
• Status: Active Grant

• Current Assignee: X Corp. (f/k/a Twitter, Inc.) (X Holdings Corp.)
• Original Assignee: International Business Machines Corporation
• Inventors: Chen, Chiahong, Blinick, Stephen LaRoux, Brewer, Scott Alan, Andre, Herve Gilbert Philippe
• Primary Examiner(s): Baderman; Scott T
• Assistant Examiner(s): PATEL, JIGAR P
• Application Number:
  US11/531,183
• Publication Number:
  US 20080126651A1
• Time in Patent Office: 1,288 Days
• Field of Search: 714/48
• US Class Current: 714/48
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 11/2089 Redundant storage control functionality

Abstract

A method of providing error notification in a storage subsystem includes writing a first defined value by a host adapter of the storage subsystem to a system management interrupt (SMI) register to generate a hardware interrupt, registering and handling the hardware interrupt by a kernel module of the storage subsystem, writing a second defined value to a shared memory location of the storage subsystem by the kernel module, and reading a shared memory offset value by the host adapter. A system for providing error notification in a storage subsystem includes a controller including a serial management interface (SMI) register subcomponent, a first processing component connected to the controller having a kernel module, and a second processing component connected to the controller executing host adapter software.

Claims

1. A method for providing error notification in a storage subsystem including a host adapter in communication with a host computing system and including a first processor and a second processor coupled to each other and to a shared memory via a controller including a system management interrupt (SMI) register, the method comprising the steps of:

detecting, by the first processor, a lack of mail communication from the second processor;

writing, by the first processor, a first defined value to the SMI register to generate a hardware interrupt in the second processor;

writing, by the second processor, a second defined value to the shared memory location in response to the hardware interrupt;

reading, by the first processor, the second defined value in the shared memory; and

disconnecting the host adapter from the host computing system, by the first processor, if the second defined value is different than a predetermined offset value.

2. The method of claim 1, wherein the detecting step occurs subsequent to a predetermined passage of time having an accompanying lack of mail communication from the second processor.

3. The method of claim 1, wherein the controller comprises a processor bridge.

4. The method of claim 1, wherein writing the first defined value to the SMI register is performed subsequent to a determination, by the first processor, of a lack of peripheral component interconnect (PCI) mail for a predetermined period of time.

5. A system for providing error notification in a storage subsystem including a host adapter in communication with a host computing device, comprising:

a shared memory device;

a controller including a system management interrupt (SMI) register subcomponent coupled to the shared memory device;

a first processor coupled to the controller, the first processor comprising a kernel module; and

a second processor coupled to the controller, the second processor executing host adapter software, wherein upon detection of an absence of peripheral component interconnect (PCI) mail communication from the first processor over a predefined period of time;

the controller writes a first defined value to the SMI register subcomponent to generate a hardware interrupt in the first processor, and

the kernel module registers the hardware interrupt, handles the hardware interrupt, and writes a second defined value to the shared memory device in response to the hardware interrupt, wherein subsequent to the kernel module writing the second defined value to the shared memory, the second defined value is read by the second processor to determine if the second defined value matches a predetermined offset value; and

disconnecting the host adapter from the host computing device, by the second processor, if the second defined value differs from a predetermined offset value.

6. The system of claim 5, wherein the controller further comprises a memory controller, PCI bridge subcomponents, or both.

7. The system of claim 6, wherein the controller further comprises a processor bridge.

8. A method of providing error notification in a storage subsystem including a host adapter coupled to a host computer system, comprising:

determining, by a first processor, a system event characterized by a lack of peripheral component interconnect (PCI) mail emanating from a second processor of the computer system over a predetermined period of time;

generating, by the first processor, a first defined value upon the system event by a host adapter of the computer system, the first defined value written to a system management interrupt (SMI) register to cause a hardware interrupt in the second processor;

registering the hardware interrupt using a kernel module located in the second processor;

writing, by the second processor, a second defined value to a shared memory location of the computer system; and

reading, by the first processor, the second defined value, wherein if the second defined value differs from a predetermined offset value, the first processor disconnects the host adapter from the host computer system.

9. The method of claim 8, wherein the SMI register is located in a controller device coupled to the first processor and the second processor.

10. The method of claim 9, wherein the controller device is configured to perform memory controller functions, PCI bridge functions, or both.

11. The method of claim 10, wherein the controller device further comprises a processor bridge.