Methods and devices for independent evaluation of cell integrity, changes and origin in chip design for production workflow

• US 7,685,545 B2
• Filed: 08/05/2009
• Issued: 03/23/2010
• Est. Priority Date: 06/10/2008
• Status: Active Grant

• Current Assignee: Oasis Tooling, Inc.
• Original Assignee: Oasis Tooling, Inc.
• Inventors: Chapman, David, Grebinski, Thomas
• Primary Examiner(s): Siek; Vuthe
• Application Number:
  US12/536,413
• Publication Number:
  US 20090307640A1
• Time in Patent Office: 230 Days
• Field of Search: 716/1, 716/4, 716/5, 716/18, 704 7- 10
• US Class Current: 716/136
• CPC Class Codes: G06F 2115/08 Intellectual property [IP] blocks or IP cores
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/3323 using formal methods, e.g. equivalence checking or property checking
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

The technology disclosed relates to granular analysis of design data used to prepare chip designs for manufacturing and to identification of similarities and differences among parts of design data files. In particular, it relates to parsing data and organizing into canonical forms, digesting the canonical forms, and comparing digests of design data from different sources, such as designs and libraries of design templates. Organizing the design data into canonical forms generally reduces the sensitivity of data analysis to variations in data that have no functional impact on the design. The details of the granular analysis vary among design languages used to represent aspects of a design. For various design languages, granular analysis includes partitioning design files by header/cell portions, by separate handling of comments, by functionally significant/non-significant data, by whitespace/non-whitespace, and by layer within a unit of design data. The similarities and differences of interest depend on the purpose of the granular analysis. The comparisons are useful in many ways.

Claims

1. A computer-implemented method of evaluating similarities and/or differences between design data for circuits, the design data residing in at least two files stored in computer memory, the method including:

using a computer, identifying cells within design data residing in first and second files, wherein the cells correspond to portions of design for a physical circuit;

parsing syntax of and normalizing the design data within the cells into canonical forms, wherein the canonical forms reduce sensitivity of data analysis to non-functional variations in the design data within a particular cell;

partitioning functionally significant design data from non-significant data within the canonical forms, wherein the design data is functionally significant when a change in the design data would result in a change in a circuit generated from the design data;

calculating and storing digests of at least selected design data in the canonical forms, producing at least one digest per cell;

wherein the selected design data in the canonical forms used to calculate the digests includes at least the functionally significant design data;

comparing the digests of the cells in the first file to the digests of the cells in the second file; and

summarizing at least some results of the comparing of the digests.

2. The method of claim 1, applied to evaluating a new library of cell designs against an old library of cell designs, wherein:

the first file is a new library of cell designs and the second file is an old library of cell designs; and

the summarizing further includes reporting at least the functionally significant changes in the new library that are detected by comparing the digests.

3. The method of claim 1, applied to detecting functionally identical cells with different cell names, wherein:

the first file is a design file and the second file is at least one approved library;

the calculating and storing digests is applied to at least functionally significant data in multiple layers of the cells in design file and the approved library; and

the summarizing further includes reporting as renamed the cells in the design file that have digests of functionally significant data in the multiple layers that do match digests of cells in the approved library (called “

the functionally matching cells”

), but which renamed cells have cell names that do not match cell names of the functionally matching cells.

4. A computer-implemented method of evaluating similarities and/or differences between design data for circuits, the design data residing in at least two files stored in computer memory, the method including:

using a computer, identifying cells within design data residing in first and second files, wherein the cells correspond to portions of design for a physical circuit;

parsing syntax of and normalizing the design data within the cells into canonical forms, wherein the canonical forms reduce sensitivity of data analysis to non-functional variations in the design data within a particular cell;

wherein

the first file contains design data expressed in an OASIS®

design language and the second file contains design data expressed in a GDSII design language; and

the canonical forms for the OASIS® and

the GDSII design languages render comparable design data in bodies of the cells;

calculating and storing digests of at least selected design data in the canonical forms, producing at least one digest per cell;

comparing the digests of the cells in the first file to the digests of the cells in the second file;

summarizing at least some results of the comparing of the digests.

5. A computer-implemented method of evaluating similarities and/or differences between design data for circuits, the design data residing in at least three files stored in computer memory, the method including:

using a computer, identifying cells within design data residing in first, second and third files, wherein the cells correspond to portions of design for a physical circuit;

wherein the first file is a design file, the second file is at least one current library of cell designs, and the third file is at least one out of date library of cell designs; and

parsing syntax of and normalizing the design data within the cells into canonical forms, wherein the canonical forms reduce sensitivity of data analysis to non-functional variations in the design data within a particular cell;

calculating and storing digests of at least selected design data in the canonical forms, producing at least one digest per cell;

comparing the digests of the cells in the first file to the digests of the cells in the second file;

reporting at least cells in the design file that have digests that do not match digests of cell designs in the current library and that do match digests of cell designs in the out of date library.

6. A computer-implemented method of evaluating similarities and/or differences between design data for circuits, the design data residing in at least two files stored in computer memory, the method including:

using a computer, identifying cells within design data residing in first and second files, wherein the cells correspond to portions of design for a physical circuit, the first file is a design file and the second file contains known bad cell designs;

parsing syntax of and normalizing the design data within the cells into canonical forms, wherein the canonical forms reduce sensitivity of data analysis to non-functional variations in the design data within a particular cell;

calculating and storing digests of at least selected design data in the canonical forms, producing at least one digest per cell;

comparing the digests of the cells in the first file to the digests of the cells in the second file; and

summarizing at least some results of the comparing of the digests; and

cells in the design file that have digests that match digests of cells in the file of known bad cell designs.

7. The method of claim 6, further applied to evaluating whether the cells in the design file belong to at least one approved library, including:

a third file to which the identifying, parsing and calculating steps are applied;

wherein the third file is at least one approved library of cells; and

wherein the summarizing further includes reporting cells in the design file that have digests that do not match digests of cells in the approved library of cells.

8. A computer-implemented method of evaluating similarities and/or differences between design data for circuits, the design data residing in at least two files stored in computer memory, the method including:

using a computer, identifying cells within design data residing in first and second files, wherein the cells correspond to portions of design for a physical circuit, the first file is a design file and the second file is at least one approved library;

parsing syntax of and normalizing the design data within the cells into canonical forms, wherein the canonical forms reduce sensitivity of data analysis to non-functional variations in the design data within a particular cell;

calculating and storing digests of at least selected design data in the canonical forms, producing at least one digest per cell;

comparing the digests of the cells in the first file to the digests of the cells in the second file; and

reporting cells in the design file that have digests that do not match digests of cells in the approved library.

9. A computer-implemented method of evaluating similarities and/or differences between design data for circuits, the design data residing in at least two files stored in computer memory, the method including:

using a computer, identifying cells within design data residing in first and second files, wherein the cells correspond to portions of design for a physical circuit, the first file is a design file and the second file is at least one approved library;

parsing syntax of and normalizing the design data within the cells into canonical forms, wherein the canonical forms reduce sensitivity of data analysis to non-functional variations in the design data within a particular cell;

calculating and storing digests of at least functionally significant data in multiple layers of the canonical forms of the cells in the design file and the approved library, producing at least one digest per cell; and

comparing the digests of the cells in the first file to the digests of the cells in the second file;

reporting as potentially modified cells in the design file that have digests of functionally significant data in some but not all of the multiple layers that match digests of cells in the approved library.

10. A computer-implemented method of evaluating similarities and/or differences between design data for circuits, the design data residing in at least two files stored in computer memory, the method including:

using a computer, identifying cells within design data residing in first and second files, wherein the cells correspond to portions of design for a physical circuit, the first file includes one or more royalty-bearing libraries of royalty-bearing cell designs and the second file includes one or more production designs that include cell designs;

parsing syntax of and normalizing the design data within the cells into canonical forms, wherein the canonical forms reduce sensitivity of data analysis to non-functional variations in the design data within a particular cell;

calculating and storing digests of at least selected design data in the canonical forms, producing at least one digest per cell;

comparing the digests of the cells in the first file to the digests of the cells in the second file; and

summarizing at least some results of the comparing of the digests;

the summarizing further includes reporting as potentially royalty-bearing cells in the production designs that have digests which match digests of cells in the royalty-bearing libraries.

11. A computer-implemented method of evaluating similarities and/or differences between design data for circuits, the design data residing in at least two files stored in computer memory, the method including:

using a computer, identifying cells within design data residing in first and second files, wherein the cells correspond to portions of design for a physical circuit;

parsing syntax of and normalizing the design data within the cells into canonical forms, wherein the canonical forms reduce sensitivity of data analysis to non-functional variations in the design data within a particular cell;

creating one or more syntax trees that partition the design data within a cell at least;

between header and body data, according to a format in which the design data is cast; and

between functionally significant and non-significant data, wherein parts of the design data are functionally significant when a change in the design data would result in a change in a circuit generated from the design data; and

calculating and storing digests of at least selected design data in the canonical forms producing at least one digest per partition per cell; and

comparing the digests of the cells in the first file to the digests of the cells in the second file;

summarizing at least some results of the comparing of the digests; and

distinguishing among the digests produced from different partition types.

12. The method of claim 11, wherein the syntax trees further partition the design data within a cell into design layers.

13. The method of claim 11, further including:

recognizing branches of the syntax trees that include nodes which represent design data that is order independent, wherein order independent means that the nodes can be processed in varying orders without changing a circuit generated from the design data represented by the nodes; and

sorting nodes in the identified branches;

wherein the calculating and storing digests are applied to the sorted nodes.

14. A device that evaluates similarities and/or differences between design data for circuits, the design data residing in at least two files stored in computer memory, the device including:

at least one processor and memory;

a parser running on the processor, that parses a file containing design data representing aspects of a design for a physical circuit and creates one or more syntax trees in the memory;

normalizer logic running on the processor and cooperating with the parser that organizes the syntax trees to produce canonical forms, wherein the normalizer logic includes;

a partitioning module that partitions the file into at least one header and, depending on rules of a design language used to encode the file, into multiple cells of design data and organizes the syntax trees to represent the header and cell partitions; and

a canonical forming module that interprets the syntax trees to produce canonical forms of the design data, wherein the canonical forms reduce sensitivity of data analysis to non-functional variations in the design data;

a digester module running on the processor that receives the canonical forms for at least selected partitions and calculates and stores in the memory at least one digest per selected partition;

a comparer module running on the processor that receives and compares the digests of at least a first file and a second file, which contain design data; and

a reporter module running on the processor and coupled to the digester that summarizes at least some of the matches and/or differences detected by the comparisons of digests.

15. The device of claim 14, wherein the canonical forming module interprets the sortability of branches of the syntax trees and organizes the syntax trees to reflect sortability.

16. The device of claim 14, wherein the partitioning module further partitions the file by layers within cells and organizes the syntax trees to reflect the layers.

17. The device of claim 14, wherein the partitioning module further partitions the file between design data that is functionally significant and design data that is not significant, wherein the design data is functionally significant when a change in the design data would result in a change in a circuit generated from the design data;

and the partitioning module organizes the syntax trees to reflect functional significance.

18. The device of claim 17, adapted to evaluating a new library of cell designs against an old library of cell designs, wherein:

the first file is a new library of cell designs and the second file is an old library of cell designs; and

the reporter module summarizes the functionally significant changes in the new library that are detected by comparing the digests.

19. The device of claim 14, wherein:

the first file includes one or more royalty-bearing libraries of royalty-bearing cell designs and the second file includes one or more production designs that include cell designs; and

the reporter module further reports as potentially royalty-bearing cells in the production designs that have digests which match digests of cells in the royalty-bearing libraries.

20. The device of claim 14, wherein:

the first file is a design file and the second file is at least one approved library;

the calculating and storing digests is applied to at least functionally significant data in multiple layers of the cells in design file and the approved library; and

the reporter module further reports as renamed the cells in the design file that have at least some digests of functionally significant data in the multiple layers that do match digests of cells in the approved library (called “

the functionally matching cells”

), but which renamed cells have cell names that do not match cell names of the functionally matching cells.