Method of fabricating a probe card

• US 7,685,705 B2
• Filed: 01/11/2008
• Issued: 03/30/2010
• Est. Priority Date: 03/26/2004
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Hunter, James A., Nulty, James E., Herrera, Alexander J.
• Primary Examiner(s): Nguyen, Donghai D.
• Application Number:
  US12/008,483
• Publication Number:
  US 20080110019A1
• Time in Patent Office: 809 Days
• Field of Search: 29830-832, 298/42, 29844-846, 298/74, 324/754, 324/755, 324/761, 324/762, 324/765, 439/66, 439/190, 439/482
• US Class Current: 29/845
• CPC Class Codes: G01R 1/07314 the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support on an elastic support, e.g. a film, G01R1/0735
• CPC Class Codes: G01R 1/0735 arranged on a flexible frame or film
• CPC Class Codes: G01R 1/07371 using an intermediate card or back card with apertures through which the probes pass
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49147 Assembling terminal to base
• CPC Class Codes: Y10T 29/49153 with shaping or forcing terminal into base aperture
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base

Abstract

A probe card for testing dice on a wafer includes a substrate, a number of cantilevers formed on a surface thereof, and a number of probes extending from unsupported ends of the cantilevers. The unsupported ends of the cantilevers project over cavities on the surface of the substrate. The probes have tips to contact pads on the dice under test. The probe card may include a compressive layer above the surface of the substrate with a number of holes through which the probes extend.

Claims

1. A method of fabricating a probe card, the method comprising:

forming a plurality of electrically conducting cantilevers on a surface of a substrate, each of the cantilevers having an unsupported end projecting over one of an equal number of cavities formed on the surface of the substrate;

forming a plurality of electrically conducting probes extending from the unsupported ends of the cantilevers, each of the probes having a tip for contacting a pad on a surface of a device under test (DUT); and

forming an electrically insulating compressive layer above the surface of the substrate, the compressive layer having a plurality of holes extending therethrough and through which the probes extend to contact pads on the surface of the DUT.

2. The method of claim 1, wherein the compressive layer is formed to a thickness equal to or less than about 300 microns.

3. The method of claim 1 wherein the compressive layer comprises polyimide and a nitride capping layer.

4. The method of claim 1 wherein each of the probes comprises a body made of a first material and having a first cross-sectional area, and a tip made of a second material and having a second cross-sectional area, and wherein the second cross-sectional area is smaller than the first cross-sectional area.

5. The method of claim 1 wherein the substrate comprises an anti-wafer having a plurality of electrically conducting wirings formed thereon for electrically coupling the probes through the electrically conductive cantilevers to a test circuit.

6. The method of claim 5 wherein the test circuit is formed in the anti-wafer.

7. The method of claim 5 wherein the substrate further comprises a gasket abutting a backside surface of the anti-wafer to increase co-planarity between the surface of the substrate and the surface of the DUT.

8. The method of claim 5 wherein the anti-wafer is divided into a plurality of probe dice, and wherein each of the probe die comprises at least one conducting cantilever projecting over a cavity formed on the surface of the probe die, and an electrically conducting probe extending from the unsupported end of the cantilever to contact a pad on a surface of a DUT on the wafer.

9. The method of claim 8 wherein the plurality of probe dice are separated from one another by a plurality of intersecting recesses, and wherein wirings to the anti-wafer are formed in the plurality of intersecting recesses to prevent scratching the wafer.