Stacked integrated circuit package system and method of manufacture therefor

• US 7,687,315 B2
• Filed: 03/10/2008
• Issued: 03/30/2010
• Est. Priority Date: 04/29/2005
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Lte.
• Original Assignee: Stats Chippac BVI limited (JCET Group Co., Ltd.)
• Inventors: Carson, Flynn
• Primary Examiner(s): Chambliss; Alonzo
• Application Number:
  US12/045,606
• Publication Number:
  US 20080169549A1
• Time in Patent Office: 750 Days
• Field of Search: None
• US Class Current: 438/109
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06558 the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1041 Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1088 Arrangements to limit the height of the assembly
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

An integrated circuit package system including providing a base substrate, attaching a base integrated circuit on the base substrate, attaching a core substrate over the base integrated circuit, attaching a substrate electrical connector between the core substrate and the base substrate, and applying an encapsulant having the core substrate partially exposed over the base integrated circuit.

Claims

1. A method of manufacture of an integrated circuit package system comprising:

providing a base substrate;

attaching a base integrated circuit over the base substrate;

attaching a core substrate over the base integrated circuit, the core substrate and a core substrate connection having sides facing the base substrate partially exposed from an attachment layer on the core substrate and the base integrated circuit;

attaching a substrate electrical connector between the core substrate and the base substrate; and

applying an encapsulant directly on a perimeter portion of a side of the core substrate opposite the base substrate and having a center portion of the side of the core substrate substantially exposed over the base integrated circuit.

2. The method as claimed in claim 1 further comprising attaching a top integrated circuit on a mounting surface of the core substrate.

3. The method as claimed in claim 1 wherein attaching the base integrated circuit comprises attaching a solder ball or a bond wire between the base integrated circuit and the base substrate.

4. The method as claimed in claim 1 wherein attaching the base integrated circuit comprises attaching another integrated circuit adjacent the base integrated circuit.

5. The method as claimed in claim 1 wherein attaching the base integrated circuit comprises attaching a base electrical connector over the base integrated circuit and part of the base substrate.

6. A method of manufacture of an integrated circuit package system comprising:

forming a base substrate having a base connection pad;

connecting a base integrated circuit with a base electrical connector over the base substrate;

attaching a core substrate on an attachment layer on the base integrated circuit, the core substrate and a core substrate connection having sides facing the base substrate partially exposed from the attachment layer;

connecting a substrate electrical connector between the core substrate and the base substrate;

forming an encapsulant over a perimeter portion at an edge of the mounting surface of the core substrate having a core connection pad exposed in a center portion of the mounting surface over the base integrated circuit; and

connecting a top electrical connector between a top integrated circuit and the core connection pad.

7. The method as claimed in claim 6 wherein connecting the base integrated circuit comprises attaching a bond wire between another integrated circuit on the base integrated circuit and the base substrate.

8. The method as claimed in claim 6 wherein connecting the base integrated circuit comprises attaching a flipchip on the base integrated circuit.

9. The method as claimed in claim 6 wherein forming the encapsulant comprises forming a mounting surface on the core substrate for a top integrated circuit.

10. The method as claimed in claim 6 wherein attaching the core substrate comprises providing the core substrate with lower routing density than routing density of the base substrate.

11. An integrated circuit package system comprising:

a base substrate;

a base integrated circuit over the base substrate;

a core substrate having a core substrate connection over the base integrated circuit;

an attachment layer on the core substrate and the base integrated circuit, the core substrate and the core substrate connection having sides facing the base substrate partially exposed from the attachment layer;

a substrate electrical connector between the core substrate and the base substrate; and

an encapsulant directly on a perimeter portion of a side of the core substrate opposite the base substrate and having a portion of the side of the core substrate substantially exposed over the base integrated circuit.

12. The system as claimed in claim 11 further comprising a top integrated circuit on a mounting surface of the core substrate.

13. The system as claimed in claim 11 further comprising a solder ball or a bond wire between the base integrated circuit and the base substrate.

14. The system as claimed in claim 11 further comprising another integrated circuit adjacent the base integrated circuit.

15. The system as claimed in claim 11 further comprising a base electrical connector over the base integrated circuit and part of the base substrate.

16. The system as claimed in claim 11 wherein:

the base substrate having a base connection pad;

the base integrated circuit with a base electrical connector over the base substrate;

the core substrate on an attachment layer over the base integrated circuit;

the substrate electrical connector between the core substrate and the base substrate;

the encapsulant over the core substrate having a core connection pad exposed over the base integrated circuit; and

further comprising;

a top electrical connector between a top integrated circuit and the core connection pad.

17. The system as claimed in claim 16 further comprising a bond wire between another integrated circuit on the base integrated circuit and the base substrate.

18. The system as claimed in claim 16 further comprising a flipchip on the base integrated circuit.

19. The system as claimed in claim 16 wherein the encapsulant comprises a mounting surface on the core substrate for a top integrated circuit.

20. The system as claimed in claim 16 wherein the core substrate comprises lower routing density than routing density of the base substrate.