Methods for manufacturing RFID tags and structures formed therefrom

• US 7,687,327 B2
• Filed: 06/12/2006
• Issued: 03/30/2010
• Est. Priority Date: 07/08/2005
• Status: Active Grant

• Current Assignee: Ensurge Micropower ASA
• Original Assignee: Kovio Incorporated (Ensurge Micropower ASA)
• Inventors: Kamath, Arvind, Cleeves, James Montague, MacKenzie, J. Devin
• Primary Examiner(s): Chaudhari; Chandra
• Assistant Examiner(s): Slutsker; Julia
• Application Number:
  US11/452,108
• Publication Number:
  US 20070007342A1
• Time in Patent Office: 1,387 Days
• Field of Search: 438/142, 438/149, 438/237, 438/190, 257/E25.01, 257/E21.35
• US Class Current: 438/149
• CPC Class Codes: G06K 19/073 Special arrangements for circuits, e.g. for protecting identification code in memory protection against unauthorised use of computer memory G06F12/14
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01L 2223/6611 Wire connections
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/142 Metallic substrates having insulating layers
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1292 using liquid deposition, e.g. printing
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Radio frequency identification (RFID) tags and processes for manufacturing the same. The RFID device generally includes (1) a metal antenna and/or inductor; (2) a dielectric layer thereon, to support and insulate integrated circuitry from the metal antenna and/or inductor; (3) a plurality of diodes and a plurality of transistors on the dielectric layer, the diodes having at least one layer in common with the transistors; and (4) a plurality of capacitors in electrical communication with the metal antenna and/or inductor and at least some of the diodes, the plurality of capacitors having at least one layer in common with the plurality of diodes and/or with contacts to the diodes and transistors. The method preferably integrates liquid silicon-containing ink deposition into a cost effective, integrated manufacturing process for the manufacture of RFID circuits. Furthermore, the present RFID tags generally provide higher performance (e.g., improved electrical characteristics) as compared to tags containing organic electronic devices.

Claims

1. A method for manufacturing integrated circuitry, comprising:

a) forming, from a first silicon-containing ink, a plurality of first semiconductor layer elements in a first pattern on a first surface of a dielectric layer, said dielectric layer on an electrically active substrate and said first semiconductor layer elements comprising a transistor channel region in a first region of the substrate, and a first diode layer element in a second region of the substrate;

b) forming, from a second silicon-containing ink, a plurality of second semiconductor layer elements different from said first semiconductor layer elements in a second pattern on at least one of said first semiconductor layer element(s) and said first surface of said dielectric layer, said second semiconductor layer elements comprising a second semiconductor layer in the first region of the substrate and a second diode layer element in the second region of the substrate, wherein at least one of said first and second semiconductor layer element forming steps comprises printing the respective first and/or second silicon-containing ink; and

c) forming a plurality of metal elements on or over said first semiconductor layer element(s) and said second semiconductor layer element(s), said metal elements comprising a metal contact and a metal gate in the first region of the substrate, and a diode contact in the second region of the substrate.

2. The method of claim 1, wherein said substrate comprises a metal foil.

3. The method of claim 2, further comprising, after said metal element forming step, the step of forming a circuit element from said metal foil.

4. The method of claim 2, further comprising, after said metal element forming step, the step of removing portions of the foil from under one or more circuit components having performance parameters adversely affected by parasitic capacitance.

5. The method of claim 1, wherein said plurality of first semiconductor layer elements further comprise at least one capacitor plates in a third region of the substrate and a plurality of first diode layers elements in the second region of the substrate.

6. The method of claim 1, wherein at least one of said first and second semiconductor layer element forming steps comprises inkjet printing a corresponding silicon-containing ink.

7. The method of claim 1, further comprising, before said metal element forming step, the step of growing an oxide on exposed surfaces of said first and second semiconductor layer elements.

8. The method of claim 1, further comprising, before said metal element forming step, the step of forming an interlayer dielectric on or over said first and second semiconductor layer elements.

9. The method of claim 8, further comprising, before said metal element forming step, the step of forming a plurality of openings in said interlayer dielectric to expose surfaces of at least some of said first and second semiconductor layer elements.

10. The method of claim 8, wherein the step of forming the interlayer dielectric comprises printing the interlayer dielectric on or over said first and second semiconductor layer elements.

11. The method of claim 1, further comprising, after said metal element forming step, the step of passivating said integrated circuitry.

12. The method of claim 1, wherein said plurality of first semiconductor layer elements comprises a plurality of first diode layers elements in the second region of the substrate and a plurality of said transistor channel regions in the first region of the substrate.

13. The method of claim 12, wherein said plurality of second semiconductor layer elements comprise (i) a plurality of second diode layer elements on said first diode layer elements and (ii) a plurality of said transistor source/drain terminals on said transistor channel regions.

27. The method of claim 1, wherein said plurality of metal elements comprise a plurality of contacts and a plurality of metal gates.

28. The method of claim 1, wherein said plurality of first semiconductor layer elements further comprise a capacitor plate in a third region of the substrate and the metal elements further comprise a second capacitor plate in the third region of the substrate.

30. The method of claim 28, wherein said plurality of metal elements comprise a plurality of contacts and a plurality of capacitor plates.

14. A method for manufacturing integrated circuitry, comprising:

a) printing, from a silicon-containing ink, a plurality of semiconductor layer elements in a pattern on a first surface of a dielectric layer, said dielectric layer on an electrically active substrate and said semiconductor layer elements comprising a transistor channel region in a first region of the substrate and a diode layer element in a second region of the substrate;

b) forming a gate layer over the transistor channel region in the first region of the substrate;

c) forming at least one dielectric layer on said gate layer, said diode layer element, and at least part of said first surface of said dielectric layer, said dielectric layer having openings for contacts to said gate layer and terminals of said plurality of semiconductor layer elements and

d) printing at least one metal element on or over the semiconductor layer elements and on said gate layer, at least some of said metal elements comprising a diode contact in the second region of the substrate and electrically connecting a first one of said terminals with a second one of said terminals and/or one of said terminals with said gate layer in the first region of the substrate.

15. The method of claim 14, further comprising, after said gate layer forming step and before said dielectric layer forming step, forming source and drain terminals on or in said semiconductor layer element(s) forming the transistor channel region.

16. A method for manufacturing integrated circuitry for a radio frequency identification (RFID) device, comprising:

a) forming, from a first semiconductor-containing ink, a plurality of first semiconductor layer elements in a first pattern on a first surface of a dielectric layer, said dielectric layer on an electrically active substrate and said first semiconductor layer elements comprising a transistor channel region in a first region of the substrate, and a first diode layer element in a second region of the substrate;

b) forming, from a second semiconductor-containing ink, plurality of second semiconductor layer elements different from said first semiconductor layer elements in a second pattern on at least one of said first semiconductor layer element(s) and said first surface of said dielectric layer, said second semiconductor layer elements comprising a second semiconductor layer in the first region of the substrate and a second diode layer element in the second region of the substrate, wherein at least one of said first and second semiconductor layer element forming steps comprises printing the respective first and/or second silicon-containing ink; and

c) forming a plurality of metal elements on or over of said first semiconductor layer element(s) and said second semiconductor layer element(s), said metal elements comprising a metal contact and a metal gate in the first region of the substrate, and a diode contact in the second region of the substrate.

17. A method for manufacturing integrated circuitry for a radio frequency identification (RFID) device, comprising:

a) printing, from a semiconductor-containing ink, a plurality of semiconductor layer elements in a pattern on a first surface of a dielectric layer, said dielectric layer on an electrically active substrate and said semiconductor layer elements comprising a transistor channel region in a first region of the substrate and a diode layer element in a second region of the substrate;

b) forming a gate layer over the transistor channel region in the first region of the substrate;

c) forming at least one dielectric layer on said gate layer, said diode layer element, and at least part of said first surface of said dielectric layer, said dielectric layer having openings for contacts to said gate layer and terminals of said plurality of semiconductor layer elements; and

d) printing at least one metal element on or over the semiconductor layer elements and on said gate layer, at least some of said metal elements comprising a diode contact in the second region of the substrate and electrically connecting a first one of said terminals with a second one of said terminals and/or one of said terminals with said gate layer in the first region of the substrate.

18. A method of manufacturing integrated circuitry, comprising:

a) forming, from a first semiconductor-containing ink, a plurality of first semiconductor layer elements in a first pattern on a first surface of a dielectric layer, said dielectric layer on an electrically active substrate, and said first semiconductor layer elements comprising a transistor channel region in a first region of the substrate, a first diode layer element in a second region of the substrate, and a first capacitor plate in a third region of the substrate;

b) forming, from a second silicon-containing ink, a plurality of second semiconductor layer elements different from said first semiconductor layer elements in a second pattern on at least one of said first semiconductor layer element(s) and said first surface of said dielectric layer, said second semiconductor layer elements comprising a second semiconductor layer in the first region of the substrate and a second diode layer element in the second region of the substrate, wherein at least one of said first and second semiconductor layer element forming steps comprises printing the respective first and/or second silicon-containing ink; and

c) forming a plurality of metal elements on or over said first semiconductor layer elements and said second semiconductor layer elements, said metal elements comprising a metal contact and a metal gate in the first region of the substrate, a diode contact in the second region of the substrate, and a second capacitor plate in the third region of the substrate.

19. The method of claim 18, further comprising, before forming said plurality of metal elements, growing an oxide on exposed surfaces of said first and second semiconductor layer elements.

20. The method of claim 18, further comprising, before forming said plurality of metal elements, forming a dielectric layer on or over said first and second semiconductor layer elements.

21. The method of claim 20, further comprising, before forming said plurality of metal elements, forming a plurality of openings in said dielectric layer to expose surfaces of at least some of said first and second semiconductor layer elements.

22. The method of claim 20, wherein forming the dielectric layer comprises printing the dielectric layer on or over said first and second semiconductor layer elements.

23. The method of claim 18, further comprising, after forming said plurality of metal elements passivating said integrated circuitry.

24. The method of claim 18, wherein printing said first semiconductor elements and said second semiconductor elements comprises inkjet printing a corresponding semiconductor-containing ink.

25. The method of claim 18, wherein said substrate comprises a metal foil.

26. The method of claim 18, wherein said plurality of first semiconductor layer elements comprise a plurality of capacitor plates and a plurality of first diode layer elements.

29. The method of claim 18, wherein said plurality of second semiconductor layer elements comprise (i) a plurality of second diode layer elements on said first diode layer elements and (ii) a plurality of said transistor channel regions on said first surface of said dielectric layer.

31. The method of claim 29, further comprising forming, from a third silicon-containing ink different from said second silicon-containing ink, at least one third semiconductor layer element in a third pattern on at least one of said second semiconductor layer element(s) in the second region of the substrate, said third semiconductor layer element comprising at least one of a third diode layer element in the second region of the substrate and transistor source/drain terminals in the first region of the substrate.

32. The method of claim 29, wherein said plurality of metal elements comprise a plurality of contacts and a plurality of transistor gates.

33. The method of claim 32, further comprising doping the transistor source/drain terminals or MOS varactors by implant, solid source, plasma or vapor introduction of dopants into said source and drain regions or MOS varactors, self-aligned to the transistor gate.