Method for manufacturing semiconductor device

• US 7,687,363 B2
• Filed: 12/15/2006
• Issued: 03/30/2010
• Est. Priority Date: 12/28/2005
• Status: Active Grant

• Current Assignee: DB HiTek Co., Ltd.
• Original Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Inventors: Ko, Choul Joo
• Primary Examiner(s): Chaudhari; Chandra
• Application Number:
  US11/639,928
• Publication Number:
  US 20070148844A1
• Time in Patent Office: 1,201 Days
• Field of Search: 438/298, 438/305, 438/529, 257/E21.63
• US Class Current: 438/298
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7836 with a significant overlap between the lightly doped extension and the gate electrode H01L29/7834, H01L29/7835 take precedence

Abstract

Disclosed is a method of manufacturing a semiconductor device, which includes the steps of: forming a high-voltage well region (e.g., by implanting impurity ions into a semiconductor substrate and then annealing); forming an isolation layer on the semiconductor substrate; implanting impurity ions into the high-voltage well region, thereby forming a low-voltage well region within the high-voltage well region; forming a gate electrode on the semiconductor substrate; and implanting impurity ions using the gate electrode as a mask, thereby forming source/drain regions within the low-voltage well region.

Claims

1. A method of manufacturing a semiconductor device, the method comprising the steps of:

forming a buffer oxide film on a semiconductor substrate;

forming a high-voltage well region in the semiconductor substrate by performing a first ion implantation at a relatively low energy, a second ion implantation at a medium energy, and a third ion implantation at a relatively high energy;

forming a pad nitride film on the buffer oxide film;

patterning the pad nitride film and the buffer oxide film and forming an isolation layer on the semiconductor substrate;

removing the patterned pad nitride film;

implanting first dopants into the high-voltage well region, thereby forming a low-voltage well region within the high-voltage well region;

forming a gate electrode on the semiconductor substrate; and

implanting second dopants into the low-voltage well region using the gate electrode as a mask, thereby forming source/drain regions within the low-voltage well region.

2. The method of claim 1, wherein forming the high-voltage well region comprises a plurality of ion implantation processes at different energies.

3. The method of claim 2, wherein the first ion implantation is performed at an energy of about 120 keV, the second ion implantation process is performed at an energy of about 200 keV and the third implantation process is performed at an energy of about 900 keV.

4. The method of claim 1, wherein the first, second and third ion implantation processes are performed with different amounts of dopants.

5. The method of claim 4, wherein the amount of dopant in the first ion implantation process is less than the amount of dopant implanted into the low-voltage well region.

6. The method of claim 1, wherein forming the high-voltage well region further comprises annealing the substrate after performing the first, second and third ion implantations.

7. The method of claim 6, wherein the annealing process includes an RTP (Rapid Thermal Process).

8. The method of claim 1, wherein a CD (Critical Dimension) of the gate electrode is 0.25 μ

m or less.

9. The method of claim 1, wherein the high-voltage well region is a high-voltage P-well, and the low-voltage well region is a low-voltage N-well.

10. The method of claim 1, wherein the high-voltage well region is a high-voltage N-well, and the low-voltage well region is a low-voltage P-well.

11. The method of claim 1, wherein the first ion implantation is performed at a relatively high dopant concentration and third ion implantation is performed at a relatively low dopant concentration.

12. The method of claim 4, wherein a dosage of the first ion implantation is approximately 5×

10¹²/cm².

13. The method of claim 4, wherein a dosage of the second ion implantation is approximately 3×

10¹²/cm².

14. The method of claim 13, wherein the low-voltage region has a relatively shallow depth with respect to the high-voltage well region.

15. The method of claim 1, wherein forming the isolation layer comprises forming a trench in exposed regions of the semiconductor substrate.

16. The method of claim 15, further comprising depositing an insulating film into the trench.

17. The method of claim 12, wherein a breakdown voltage of the low-voltage well region exceeds 20 V.