Front-end processed wafer having through-chip connections

• US 7,687,397 B2
• Filed: 04/05/2007
• Issued: 03/30/2010
• Est. Priority Date: 06/06/2006
• Status: Active Grant

• Current Assignee: Cufer Asset Ltd LLC (Intellectual Ventures LLC)
• Original Assignee: Cufer Asset Ltd LLC (Intellectual Ventures LLC)
• Inventors: Trezza, John
• Primary Examiner(s): EVERHART, CARIDAD
• Application Number:
  US11/696,799
• Publication Number:
  US 20070281466A1
• Time in Patent Office: 1,090 Days
• Field of Search: 438/667, 438/18, 257/E21.521, 257/E21.529, 257/E21.597
• US Class Current: 438/667
• CPC Class Codes: B81C 1/00095 Interconnects
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate

Abstract

A method involves forming vias in a device-bearing semiconductor wafer, making at least some of the vias in the device-bearing semiconductor wafer electrically conductive, and performing back-end processing the device-bearing semiconductor wafer so as to create electrical connections between an electrically conductive via and a metallization layer. An alternative method involves forming vias in a device-bearing semiconductor wafer, making at least some of the vias in the device-bearing semiconductor wafer electrically conductive, and processing the device-bearing semiconductor wafer so as to create electrical connections between an electrically conductive via and a conductive semiconductor layer.

Claims

1. A method of processing a semiconductor wafer comprising:

forming a plurality of vias in a semiconductor wafer;

making at least some of the plurality of vias electrically conductive;

forming a metallization layer over the plurality of vias using the same process used to make at least some of the plurality of vias electrically conductive;

performing back-end processing on the semiconductor wafer after said forming a metallization layer; and

performing intermediate device testing during said performing back-end processing.

2. The method of claim 1, wherein said making at least some of the plurality of vias electrically conductive comprises disposing one of a metal, a metal alloy, or a polysilicon material in a via.

3. The method of claim 1, wherein the semiconductor wafer is a blank wafer and the method further comprises forming devices on the semiconductor wafer after said forming a plurality of vias and said making at least some of the plurality of vias electrically conductive.

4. The method of claim 1, wherein said disposing is performed substantially concurrently with said forming a metallization layer.

5. The method of claim 4, wherein said disposing comprises:

applying a solid photoresist to the semiconductor wafer;

patterning the solid photoresist;

applying a seed layer to areas exposed by said patterning; and

plating the seed layer to dispose a plating material in the via and to form the metallization layer.

6. The method of claim 5, wherein said applying a solid photoresist comprises applying a solid photoresist over at least one via so that the via will not be filled with the plating material during said plating the seed layer.

7. The method of claim 1, wherein the metallization layer is an Nth metal layer, wherein N is an integer between 1 and 12.

8. The method of claim 7, further comprising filling a via subsequent to formation of at least one metallization layer.

9. The method of claim 1, wherein the semiconductor wafer is a device-bearing semiconductor wafer and the method further comprises performing back-end processing on the device-bearing semiconductor wafer after said making at least some of the plurality of vias electrically conductive.

10. The method of claim 9, wherein said performing back-end processing comprises forming a metal-X layer through a plating process, where X is an integer.

11. A method of processing a semiconductor wafer comprising:

forming a plurality of vias in a semiconductor wafer;

making at least some of the plurality of vias electrically conductive; and

forming a metallization layer over the plurality of vias using the same process used to make at least some of the plurality of vias electrically conductive;

wherein said forming a plurality of vias comprises forming an annular via.

12. The method of claim 11, wherein said forming an annular via comprises forming the annular via partially through the semiconductor wafer.

13. The method of claim 12, further comprising filling the annular via with an electrically conductive material.

14. The method of claim 13, further comprising removing a central post surrounded by the annular via.

15. The method of claim 12, wherein said making at least some of the plurality of vias electrically conductive comprises:

filling the annular via with an insulator; and

doping a central post surrounded by the annular via to make the central post electrically conductive.

16. The method of claim 15, wherein said doping is performed in a front-end process, the method further comprising removing a bottom portion of the semiconductor wafer.

17. A method of processing a device-bearing semiconductor wafer comprising:

forming a plurality of vias in the device-bearing semiconductor wafer;

making at least some of the plurality of vias electrically conductive;

forming a metallization layer over the plurality of vias using the same process used to make at least some of the plurality of vias electrically conductive;

performing back-end processing on the device-bearing semiconductor wafer after said making at least some of the plurality of vias electrically conductive; and

stopping said performing back-end processing for intermediate device testing.