Inverter

• US 7,687,807 B2
• Filed: 08/06/2007
• Issued: 03/30/2010
• Est. Priority Date: 09/29/2006
• Status: Expired due to Fees

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Ku, Chan Hoe, Koo, Jae Bon, Lim, Sang Chul, Kim, Seong Hyun, Suh, Kyung Soo, Lee, Jung Hun
• Primary Examiner(s): Tran; Minh-Loan T
• Assistant Examiner(s): Sengdara; Vongsavanh
• Application Number:
  US11/834,044
• Publication Number:
  US 20080080221A1
• Time in Patent Office: 967 Days
• Field of Search: 257/40, 257/59, 257/72, 257/347, 257/348, 257/350, 257/351, 257/E51.006, 257/E29.117, 257/E29.137, 257/E29.29, 257/E29.291, 257/E29.293, 257/E29.294
• US Class Current: 257/59
• CPC Class Codes: H10K 19/10 comprising field-effect transistors
• CPC Class Codes: H10K 19/201 Integrated devices having a three-dimensional layout, e.g. 3D ICs

Abstract

Provided are a structure and fabricating method of a new inverter for controlling a threshold voltage of each location when an inverter circuit is manufactured using an organic semiconductor on a plastic substrate.

In general, p-type organic semiconductor is stable. Accordingly, when the inverter is formed of only the p-type semiconductor, a D-inverter composed of a depletion load and an enhancement driver has large gains, wide swing width and low power consumption, which is more preferable than an E-inverter composed of an enhancement load and an enhancement driver. However, it is impossible to form a depletion transistor and an enhancement transistor on the same substrate while controlling them by locations.

To overcome such a difficulty, the structure of the inverter in which a bottom gate organic semiconductor transistor showing enhancement type characteristics is used as a driver transistor, and a top gate organic semiconductor transistor showing depletion type characteristics is used as a load transistor, and a manufacturing method thereof are proposed. According to this structure, a passivation effect of an organic semiconductor may be additionally obtained by a second insulating layer and a second gate electrode material which are on top of the organic semiconductor, and a high degree of integration may also be improved.

Claims

1. An inverter, comprising:

a driver transistor having a bottom gate transistor structure; and

a load transistor having a top gate transistor structure,

wherein the inverter has a structure of a D-inverter,

wherein a single electrode forms both a drain electrode of the driver transistor and a source electrode of the load transistor and the single electrode is electrically and directly connected to a gate electrode of the load transistor, and

wherein channels of the driver transistor and the load transistor are only formed by one type, either n-type or p-type.

2. The inverter according to claim 1, wherein a drain electrode of the driver transistor and a source electrode of the load transistor are formed of the same layer.

3. The inverter according to claim 1, wherein the driver transistor and the load transistor are organic semiconductor transistors.

4. The inverter according to claim 1, wherein, in the driver transistor, a source is connected to a ground voltage, an input signal is applied to a gate, and a drain is connected to a source of the load transistor, and in the load transistor, a gate and the source are connected to each other and a drain is connected to a power supply voltage.

5. The inverter according to claim 1, wherein the driver transistor and the load transistor have the same width/length (W/L).

6. The inverter according to claim 1, wherein the load transistor has a double gate structure of a bottom gate and a top gate.

7. The inverter according to claim 6, wherein a drain electrode of the driver transistor is electrically and directly connected to a bottom gate electrode of the load transistor, and the drain electrode of the driver transistor is electrically and directly connected to a top gate electrode of the load transistor.

8. The inverter according to claim 7, wherein the drain electrode of the driver transistor and the source electrode of the load transistor are formed of the same layer.

9. The inverter according to claim 6, wherein a drain electrode of the driver transistor and the bottom and top gate electrodes of the load transistor are electrically connected through a contact hole.

10. The inverter according to claim 1, wherein a top gate electrode of the load transistor is formed of at least one of titanium (Ti), copper (Cu), chromium (Cr), aluminum (Al), aurum (Au), molybdenum (Mo) and tungsten (W), indium tin oxide (ITO), indium zinc oxide (IZO), or poly(3,4-ethylenedioxythiophene) (PEDOT).

11. The inverter according to claim 1, wherein source and drain electrodes of the driver transistor and the load transistor are formed of at least one of Au, platinum (Pt), nickel (Ni) and palladium (Pd), ITO, IZO, or PEDOT.

12. The inverter according to claim 1, wherein a hydrophobic surface treatment process is applied to a first insulating layer forming a bottom gate upper channel of the driver transistor using octadecyltrichiorosilane (OTS), hexamethyldisllazane (HMDS), etc., and the surface treatment is not applied to a second insulating layer forming a top gate lower channel of the load transistor.

13. An inverter, comprising:

a gate electrode of a driver transistor formed on a substrate;

a first insulating layer covering the gate electrode of the driver transistor;

a source electrode of a driver transistor, a single electrode forming both a drain electrode of the driver transistor and a source electrode of a load transistor, and a drain electrode of the load transistor, all of them are formed on the first insulating layer;

an organic semiconductor layer formed on the first insulating layer exposed between the source and drain electrodes;

a second insulating layer covering the source and drain electrodes and the organic semiconductor layer; and

a top gate electrode of the load transistor formed on the second insulating layer, and electrically and directly connected to the single electrode.

14. The inverter according to claim 13, wherein, in the second insulating layer, a contact hole for electrically connecting the top gate electrode of the load transistor and the single electrode is formed.

15. The inverter according to claim 13, further comprising a bottom gate electrode of the load transistor formed of the same layer as the gate electrode of the driver transistor.

16. The inverter according to claim 15, wherein, in the first insulating layer, a contact hole for electrically and directly connecting the bottom gate electrode of the load transistor and the single electrode is formed.

17. The inverter according to claim 13, wherein the substrate is a plastic substrate.