Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys
First Claim
1. A junction field effect transistor (JFET), comprising:
- a source region of a first conductivity type;
a drain region of the first conductivity type which is spaced apart from the source region;
a channel region of the first conductivity type which is located between the source and drain regions, wherein the channel region has a maximum length of less than 100 nm;
a gate region of a second conductivity type which is formed on top of the channel region;
a gate electrode region of the second conductivity type which overlays the gate region, wherein the gate electrode region comprises a high band gap material; and
wherein the high band gap material facilitates a faster switching speed and lower power consumption of the JFET as compared to a different JFET that does not use the high band gap material in the gate electrode region.
3 Assignments
0 Petitions
Accused Products
Abstract
This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices.
-
Citations
57 Claims
-
1. A junction field effect transistor (JFET), comprising:
-
a source region of a first conductivity type; a drain region of the first conductivity type which is spaced apart from the source region; a channel region of the first conductivity type which is located between the source and drain regions, wherein the channel region has a maximum length of less than 100 nm; a gate region of a second conductivity type which is formed on top of the channel region; a gate electrode region of the second conductivity type which overlays the gate region, wherein the gate electrode region comprises a high band gap material; and wherein the high band gap material facilitates a faster switching speed and lower power consumption of the JFET as compared to a different JFET that does not use the high band gap material in the gate electrode region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
-
-
23. A junction field effect transistor, comprising:
-
a semiconductor substrate; a source region of a first conductivity type which is formed in the substrate; a drain region of the first conductivity type which is formed in the substrate and spaced apart from the source region; a channel region of the first conductivity type which is located between the source and drain regions, wherein the channel region has a maximum length of less than 100 nm; a gate electrode region of a second conductivity type which overlays the semiconductor substrate, wherein at least a portion of the gate electrode region comprises a polycrystalline alloy comprising at least silicon and carbon; and a gate region of the second conductivity type which is formed in the substrate. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48)
-
-
49. An electronic circuit comprising one or more devices wherein at least one device in the electronic circuit comprises a junction field effect transistor that comprises:
-
a source region of a first conductivity type; a drain region of the first conductivity type which is spaced apart from the source region; a channel region of the first conductivity type which is located between the source and drain regions, wherein the channel region has a maximum length of less than 100 nm; a gate region of a second conductivity type which is formed on top of the channel region; a gate electrode region of the second conductivity type which overlays the gate region, wherein the gate electrode region comprises a high band gap material; and wherein the high band gap material facilitates a faster switching speed and lower power consumption of the JFET as compared to a different JFET that does not use the high band gap material in the gate electrode region. - View Dependent Claims (50, 51, 52, 53, 54, 55, 56, 57)
-
Specification