Memory utilizing oxide-conductor nanolaminates

• US 7,687,848 B2
• Filed: 07/31/2006
• Issued: 03/30/2010
• Est. Priority Date: 07/08/2002
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard
• Primary Examiner(s): Tran; Thien F
• Application Number:
  US11/496,196
• Publication Number:
  US 20090218612A1
• Time in Patent Office: 1,338 Days
• Field of Search: 257315-317, 257/319, 257/321
• US Class Current: 257/316
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Structures, systems and methods for floating gate transistors utilizing oxide-conductor nanolaminates are provided. One floating gate transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A floating gate is separated from the channel region by a first gate oxide. The floating gate includes oxide-conductor nanolaminate layers to trap charge in potential wells formed by different electron affinities of the oxide-conductor nanolaminate layers.

Claims

1. A vertical memory cell, comprising:

a vertical floating gate transistor extending outwardly from a substrate, the floating gate transistor having a source region, a drain region, a channel region between the source and the drain regions, and a floating gate separated from the channel region by a gate insulator, wherein the floating gate region includes oxide-conductor nanolaminate layers, wherein the nanolaminate layers include at least one charge storage layer;

a sourceline located beneath the vertical floating gate transistor, and coupled to the source region;

a transmission line coupled to the drain region; and

circuitry coupled to the vertical floating gate transistor to program the transistor in a reverse direction, and to read the transistor in a forward direction.

2. The vertical memory cell of claim 1, wherein the charge storage layer includes Tantalum Nitride (TaN).

3. The vertical memory cell of claim 1, wherein the charge storage layer includes Titanium Nitride (TiN).

4. The vertical memory cell of claim 1, wherein the charge storage layer includes Tungsten Nitride(WN).

5. The vertical memory cell of claim 1, wherein the charge storage layer includes Niobium Nitride (NbN).

6. The vertical memory cell of claim 1, wherein the charge storage layer includes Molybdenum Nitride (MoN).

7. The vertical memory cell of claim 1, wherein the charge storage layer includes Zinc-Oxide-Silicon (ZnOS).

8. The vertical memory cell of claim 1, wherein the charge storage layer includes Tungsten (W).

9. The vertical memory cell of claim 1, wherein the charge storage layer includes Nickel (Ni).

10. A vertical memory cell, comprising:

a vertical floating gate transistor extending outwardly from a substrate, the floating gate transistor having a source region, a drain region, a channel region between the source region and the drain region, a floating gate separated from the channel region by a first gate oxide, and a control gate separated from the floating gate by a second gate oxide, wherein the floating gate region includes oxide-conductor nanolaminate layers, wherein the nanolaminate layers include at least one charge storage layer;

a wordline coupled to the control gate;

a sourceline formed in a trench adjacent to the vertical floating gate transistor, wherein the source region is coupled to the sourceline;

a bit line coupled to the drain region; and

circuitry coupled to the vertical floating gate transistor to program the transistor in a reverse direction, and to read the transistor in a forward direction.

11. The vertical memory cell of claim 10, wherein the charge storage layer includes Tantalum Nitride (TaN).

12. The vertical memory cell of claim 10, wherein the charge storage layer includes Titanium Nitride (TiN).

13. The vertical memory cell of claim 10, wherein the charge storage layer includes Tungsten Nitride (WN).

14. The vertical memory cell of claim 10, wherein the charge storage layer includes Niobium Nitride (NbN).

15. The vertical memory cell of claim 10, wherein the charge storage layer includes Molybdenum Nitride (MoN).

16. The vertical memory cell of claim 10, wherein at least one of the oxide-conductor nanolaminate layers are formed by atomic layer deposition (ALD).

17. A vertical memory cell, comprising:

a vertical floating gate transistor extending outwardly from a substrate, the floating gate transistor having a source region, a drain region, a channel region between the source region and the drain region, a floating gate separated from the channel region by a first gate oxide, and a control gate separated from the floating gate by a second gate oxide, wherein the floating gate region includes oxide-conductor nanolaminate layers, wherein the nanolaminate layers include at least one doped oxide charge storage layer;

a wordline coupled to the control gate;

a sourceline formed in a trench adjacent to the vertical floating gate transistor, wherein the source region is coupled to the sourceline;

a bit line coupled to the drain region; and

circuitry coupled to the vertical floating gate transistor to program the transistor in a reverse direction, and to read the transistor in a forward direction.

18. The vertical memory cell of claim 17, wherein the doped oxide charge storage layer includes Zinc-Oxide-Silicon (ZnOS).

19. A vertical memory cell, comprising:

a vertical floating gate transistor extending outwardly from a substrate, the floating gate transistor having a source region, a drain region, a channel region between the source region and the drain region, a floating gate separated from the channel region by a first gate oxide, and a control gate separated from the floating gate by a second gate oxide, wherein the floating gate region includes oxide-conductor nanolaminate layers, wherein the nanolaminate layers include at least one layer of a metal conductor;

a wordline coupled to the control gate;

a sourceline formed in a trench adjacent to the vertical floating gate transistor, wherein the source region is coupled to the sourceline;

a bit line coupled to the drain region; and

circuitry coupled to the vertical floating gate transistor to program the transistor in a reverse direction, and to read the transistor in a forward direction.

20. The vertical memory cell of claim 19, wherein the metal conductor includes Tungsten (W).

21. The vertical memory cell of claim 19, wherein the metal conductor includes Nickel (Ni).