System and method for ESD protection

• US 7,687,858 B2
• Filed: 01/03/2008
• Issued: 03/30/2010
• Est. Priority Date: 01/15/1999
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Lu, Fang, Woo, Agnes N., Kindsfater, Kenneth R.
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US12/003,929
• Publication Number:
  US 20080174925A1
• Time in Patent Office: 817 Days
• Field of Search: 257/355, 257/356, 257/357, 257/360
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H03D 1/22 Homodyne or synchrodyne circuits receiver circuits H04B1/30
• CPC Class Codes: H03G 1/0005 Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
• CPC Class Codes: H03H 11/1291 Current or voltage controlled filters
• CPC Class Codes: H03J 2200/10 Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03J 2200/18 Tuning of a master filter in order to tune its slave filter
• CPC Class Codes: H03J 3/08 by varying a second parameter simultaneously with the tuning, e.g. coupling bandpass filter
• CPC Class Codes: H03K 17/164 using parallel switching arrangements
• CPC Class Codes: H03K 2217/96015 Constructional details for touch switches for capacitive touch switches see H03K2217/9607
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.

Claims

1. An electrostatic discharge (ESD) protection system for an integrated circuit die that includes a circuit core and a plurality of bond pads surrounding the circuit core, comprising:

a localized power supply bus disposed within the circuit core;

a localized ground bus disposed within the circuit core;

a power supply ring disposed in an area between the plurality of bond pads and a periphery of the integrated circuit die; and

an ESD clamp coupled between the localized power supply bus and the power supply ring for providing a low impedance discharge path between the localized power supply bus and the power supply ring, wherein the ESD clamp is disposed between two adjacent bond pads.

2. The ESD protection system of claim 1, wherein the ESD clamp is non-overlapping with respect to the two adjacent bond pads.

3. The ESD protection system of claim 1, further comprising a second ESD clamp coupled between the localized power supply bus and the localized ground bus.

4. The ESD protection system of claim 3, wherein the second ESD clamp comprises a pair of anti-parallel diodes.

5. The ESD protection system of claim 3, further comprising a ground ring disposed in an area between the plurality of bond pads and the periphery of the integrated circuit die.

6. The ESD protection system of claim 1, wherein a bond pad in the plurality of bond pads is coupled to the localized power supply bus.

7. The ESD protection system of claim 6, wherein the bond pad is coupled to a circuit external to the periphery of the integrated circuit die.

8. The ESD protection system of claim 1, wherein a bond pad in the plurality of bond pads is coupled to the localized ground bus.

9. The ESD protection system of claim 8, wherein the bond pad is coupled to a circuit external to the periphery of the integrated circuit die.

10. The ESD protection system of claim 1, wherein a bond pad in the plurality of bond pads is coupled to the power supply ring.

11. The ESD protection system of claim 10, wherein the bond pad is coupled to a circuit external to the periphery of the integrated circuit die.

12. The ESD protection system of claim 1, wherein the ESD clamp comprises a pair of anti-parallel diodes.

13. The ESD protection system of claim 1, wherein the power supply ring is coupled to a pin of an integrated circuit package.

14. The ESD protection system of claim 1, wherein the plurality of bond pads is staggered.

15. The ESD protection system of claim 5, further comprising a second ESD clamp coupled between the localized ground bus and the ground ring.

16. The ESD protection system of claim 15, wherein the second ESD clamp comprises a pair of anti-parallel diodes.

17. The ESD protection system of claim 15, wherein the second ESD clamp is disposed between two adjacent bond pads.

18. The ESD protection system of claim 1, further comprising a shunt transistor coupled between said power supply ring and a bond pad.

19. The ESD protection system of claim 1, wherein said power supply ring is at a non-zero potential.

20. An electrostatic discharge (ESD) protection system for an integrated circuit die that includes a circuit core and a plurality of bond pads surrounding the circuit core, comprising:

a localized power supply bus disposed within the circuit core;

a localized ground bus disposed within the circuit core;

a partial power supply ring structure disposed in an area between the plurality of bond pads and a periphery of the integrated circuit die;

wherein the partial power supply ring structure includes a first terminating point and a second terminating point, the first and second terminating points forming a gap for preventing an eddy current; and

an ESD clamp coupled between the localized power supply bus and the partial power supply ring structure for providing a low impedance discharge path between the localized power supply bus and the partial power supply ring structure, wherein the ESD clamp is disposed between two adjacent bond pads.

21. The ESD protection system of claim 20, wherein the ESD clamp is non-overlapping with respect to the two adjacent bond pads.

22. The ESD protection system of claim 20, further comprising a second ESD clamp coupled between the localized power supply bus and the localized ground bus.

23. The ESD protection system of claim 20, wherein the second ESD clamp comprises a pair of anti-parallel diodes.

24. The ESD protection system of claim 20, wherein a bond pad in the plurality of bond pads is coupled to the localized power supply bus.

25. The ESD protection system of claim 24, wherein the bond pad is coupled to a circuit external to the periphery of the integrated circuit die.

26. The ESD protection system of claim 20, wherein a bond pad in the plurality of bond pads is coupled to the localized ground bus.

27. The ESD protection system of claim 26, wherein the bond pad is coupled to a circuit external to the periphery of the integrated circuit die.

28. The ESD protection system of claim 20, wherein a bond pad in the plurality of bond pads is coupled to the partial power supply ring structure.

29. The ESD protection system of claim 28, wherein the bond pad is coupled to a circuit external to the periphery of the integrated circuit die.

30. The ESD protection system of claim 20, wherein the ESD clamp comprises a pair of anti-parallel diodes.

31. The ESD protection system of claim 20, wherein the partial power supply ring structure is coupled to a pin of an integrated circuit package.

32. The ESD protection system of claim 20, wherein the plurality of bond pads is staggered.

33. The ESD protection system of claim 20, further comprising a shunt transistor coupled between said partial power supply ring structure and a bond pad.

34. The ESD protection system of claim 20, wherein said partial power supply ring structure is at a non-zero potential.

35. The ESD protection system of claim 20, further comprising a partial ground ring structure disposed in an area between the plurality of bond pads and the periphery of the integrated circuit die, and a second ESD clamp coupled between the localized ground bus and the partial ground ring structure.