Dual laminate package structure with embedded elements

• US 7,687,899 B1
• Filed: 08/07/2007
• Issued: 03/30/2010
• Est. Priority Date: 08/07/2007
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Berry, Christopher J.
• Primary Examiner(s): Geyer; Scott B
• Application Number:
  US11/835,235
• Time in Patent Office: 966 Days
• Field of Search: None
• US Class Current: 257/687
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32013 the layer connector being larger than the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06548 Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1041 Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

An interconnect structure (i.e., an interposer) which is mounted and electrically connected to a bottom semiconductor package substrate either prior or subsequent to such bottom substrate being populate with one or more electronic components. Subsequently, a top semiconductor package substrate which may also be populated with one or more electronic components is mounted to the interposer, such that all of the electronic components are disposed between the top and bottom interposers. Thereafter, a suitable mold compound is injected between the top and bottom substrates, the mold compound flowing about the electronic components, between the BGA joints, and at least partially about the interposer, thus helping to lock the interposer in place in the completed semiconductor package.

Claims

1. A semiconductor package comprising:

a bottom substrate including;

opposed top and bottom substrate surfaces;

a plurality of top contacts disposed on the top substrate surface; and

a plurality of bottom contacts disposed on the bottom substrate surface, each of the bottom contacts being electrically connected to at least one of the top contacts;

at least one electronic component attached to the top substrate surface of the bottom substrate and electrically connected to at least one the top contacts;

an interposer electrically connected to at least some of the top contacts of the bottom substrate;

a top substrate including;

opposed top and bottom substrate surfaces;

a plurality of top contacts disposed on the top substrate surface; and

a plurality of bottom contacts disposed on the bottom substrate surface, each of the top contacts being electrically connected to at least one of the bottom contacts, with at least some of the bottom contacts being electrically connected to the interposer; and

a package body defining a side surface, the package body at least partially encapsulating the top and bottom substrates, the interposer and the electronic component such that at least the bottom substrate surface of the bottom substrate and the top substrate surface of the top substrate are not covered by the package body.

2. The semiconductor package of claim 1 wherein a plurality of electronic components are attached to the top substrate surface of the bottom substrate in a stacked arrangement, each of the electronic components being electrically connected to at least one of the top contacts of the bottom substrate and encapsulated by the package body.

3. The semiconductor package of claim 1 wherein the interposer comprises:

an interposer body defining opposed top and bottom interposer surfaces;

a plurality of top pads disposed on the top interposer surface and electrically connected to respective ones of at least some of the bottom contacts of the top substrate;

a plurality of bottom pads disposed on the bottom interposer surface and electrically connected to respective ones of at least some of the top contacts of the bottom substrate; and

a plurality of conductive vias extending through the interposer body and electrically connecting each of the top pads to at least one of the bottom pads.

4. The semiconductor package of claim 3 wherein the interposer body further defines at least one side surface segment which is exposed in the side surface of the package body.

5. The semiconductor package of claim 3 wherein each of the bottom pads is electrically connected to a respective one of the top contacts of the bottom substrate by a solder ball which is covered by the package body, and each of the top pads is electrically connected to a respective one of the bottom contacts of the top substrate by a solder ball which is covered by the package body.

6. The semiconductor package of claim 1 further comprising at least one electronic component attached to the bottom substrate surface of the top substrate and electrically connected to at least some the bottom contacts of the top substrate, each of the electronic components of the semiconductor package being covered by the package body.

7. The semiconductor package of claim 1 wherein:

the bottom and top substrates each have a generally quadrangular configuration defining multiple peripheral edge segments;

the top contacts of the bottom substrate are segregated into at least two sets which extend along respective ones of at least two of the peripheral edge segments of the bottom substrate;

the bottom contacts of the top substrate are segregated into at least two sets which extend along respective ones of at least two of the peripheral edge segments of the top substrate; and

the interposer comprises separate first and second segments which are electrically connected to respective ones of the sets of the top contacts of the bottom substrate and the bottom contacts of the top substrate.

8. The semiconductor package of claim 7 wherein the first and second segments of the interposer each comprise:

an interposer body defining opposed top and bottom interposer surfaces;

a plurality of top pads disposed on the top interposer surface and electrically connected to respective ones of at least some of the bottom contacts of the top substrate;

a plurality of bottom pads disposed on the bottom interposer surface and electrically connected to respective ones of at least some of the top contacts of the bottom substrate; and

a plurality of conductive vias extending through the interposer body and electrically connecting each of the top pads to at least one of the bottom pads.

9. The semiconductor package of claim 1 wherein the electronic component comprises at least one semiconductor die which is electrically connected to at least some of the top contacts of the bottom substrate by conductive wires which are covered by the package body.

10. The semiconductor package of claim 1 wherein the each of the bottom contacts of the bottom substrate includes a solder bump formed thereon.

11. A semiconductor package comprising:

a bottom substrate including;

opposed top and bottom substrate surfaces;

a plurality of top contacts disposed on the top substrate surface; and

a plurality of bottom contacts disposed on the bottom substrate surface, each of the bottom contacts being electrically connected to at least one of the top contacts;

a top substrate including;

opposed top and bottom substrate surfaces;

a plurality of top contacts disposed on the top substrate surface; and

a plurality of bottom contacts disposed on the bottom substrate surface, each of the top contacts being electrically connected to at least one of the bottom contacts;

at least one electronic component attached to the top substrate surface of the bottom substrate and electrically connected to at least some the top contacts of the bottom substrate;

a means for electrically connecting at least some of the top contacts of the bottom substrate to at least some of the bottom contacts of the top substrate; and

a package body defining a side surface, the package body at least partially encapsulating the top and bottom substrates, the electrical connection means and the electronic component such that at least the bottom substrate surface of the bottom substrate and the top substrate surface of the top substrate are not covered by the package body.

12. The semiconductor package of claim 11 wherein at least one electronic component is attached to the bottom substrate surface of the top substrate and electrically connected to at least some of the bottom contacts of the top substrate, each of the electronic components of the semiconductor package being encapsulated by the package body.

13. The semiconductor package of claim 11 wherein the electrical connection means comprises an interposer having:

an interposer body defining opposed top and bottom interposer surfaces;

a plurality of top pads disposed on the top interposer surface and electrically connected to respective ones of at least some of the bottom contacts of the top substrate;

a plurality of bottom pads disposed on the bottom interposer surface and electrically connected to respective ones of at least some of the top contacts of the bottom substrate; and

a plurality of conductive vias extending through the interposer body and electrically connecting each of the top pads to at least one of the bottom pads.

14. The semiconductor package of claim 13 wherein the interposer body further defines at least one side surface segment which is exposed in the side surface of the package body.

15. The semiconductor package of claim 13 wherein each of the bottom pads is electrically connected to a respective one of the top contacts of the bottom substrate by a solder ball which is covered by the package body, and each of the top pads is electrically connected to a respective one of the bottom contacts of the top substrate by a solder ball which is covered by the package body.

16. The semiconductor package of claim 13 wherein:

the bottom and top substrates each have a generally quadrangular configuration defining multiple peripheral edge segments;

the top contacts of the bottom substrate are segregated into at least two sets which extend along respective ones of at least two of the peripheral edge segments of the bottom substrate;

the bottom contacts of the top substrate are segregated into at least two sets which extend along respective ones of at least two of the peripheral edge segments of the top substrate; and

the interposer comprises separate first and second segments which are electrically connected to respective ones of the sets of the top contacts of the bottom substrate and the bottom contacts of the top substrate.

17. The semiconductor package of claim 16 wherein the first and second segments of the interposer each comprise:

an interposer body defining opposed top and bottom interposer surfaces;

a plurality of top pads disposed on the top interposer surface and electrically connected to respective ones of at least some of the bottom contacts of the top substrate;

a plurality of bottom pads disposed on the bottom interposer surface and electrically connected to respective ones of at least some of the top contacts of the bottom substrate; and

a plurality of conductive vias extending through the interposer body and electrically connecting each of the top pads to at least one of the bottom pads.

18. The semiconductor package of claim 13 wherein:

the bottom and top substrates each have a generally quadrangular configuration defining multiple peripheral edge segments;

the top contacts of the bottom substrate are segregated into at least three sets, with two of the sets extending along respective ones of at least two of the peripheral edge segments of the bottom substrate and one of the sets extending between the two remaining sets;

the bottom contacts of the top substrate are segregated into at least three sets, with two of the sets extending along respective ones of at least two of the peripheral edge segments of the top substrate and one of the sets extending between the two remaining sets; and

the interposer comprises separate first, second and third segments which are electrically connected to respective ones of the sets of the top contacts of the bottom substrate and the bottom contacts of the top substrate, the third segment of the interposer effectively separating at least two of the electronic components from each other.

19. The semiconductor package of claim 18 wherein the first, second and third segments of the interposer each comprise:

an interposer body defining opposed top and bottom interposer surfaces;

a plurality of top pads disposed on the top interposer surface and electrically connected to respective ones of at least some of the bottom contacts of the top substrate;

a plurality of bottom pads disposed on the bottom interposer surface and electrically connected to respective ones of at least some of the top contacts of the bottom substrate; and

a plurality of conductive vias extending through the interposer body and electrically connecting each of the top pads to at least one of the bottom pads.

20. The semiconductor package of claim 11 further comprising a plurality of electronic components attached to the bottom substrate surface of the top substrate and electrically connected to at least some the bottom contacts of the top substrate, at least two of the electronic components attached to the bottom substrate surface of the top substrate being separated from each other by the electrical connection means.